R1LV0208BSA
R10DS0050EJ0100 Rev.1.00 Page 8 of
13
2011.03.30
Write Cycle
R1LV0208BSA-5S* R1LV0208BSA-7S*
Parameter Symbol
Min. Max. Min. Max.
Unit Note
Write cycle time t
WC
55 - 70 - ns
Address valid to end of write t
AW
50 - 55 - ns
Chip select to end of write t
CW
50 - 55 - ns 5
Write pulse width t
WP
45 - 50 - ns 4
Address setup time t
AS
0 - 0 - ns 6
Write recovery time t
WR
0 - 0 - ns 7
Data to write time overlap t
DW
25 - 30 - ns
Data hold from write time t
DH
0 - 0 - ns
Output enable from end of write t
OW
5 - 5 - ns 2
Output disable to output in high-Z t
OHZ
0 20 0 25 ns 1,2
Write to output in high-Z t
WHZ
0 20 0 25 ns 1,2
Note 1. t
CHZ
, t
OHZ
and t
WHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not
referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, t
HZ
max is less than t
LZ
min both for a given device and from
device to device.
4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE#.
A write begins at the latest transition among CS1# going low, CS2 going high and WE# going low.
A write ends at the earliest transition among CS1# going high, CS2 going low and WE# going high.
t
WP
is measured from the beginning of write to the end of write.
5. t
CW
is measured from the later of CS1# going low or CS2 going high to end of write.
6. t
AS
is measured the address valid to the beginning of write.
7. t
WR
is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle.
8. Don’t apply inverted phase signal externally when DQ pin is output mode.
