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AD7396AR-REEL

P1-P3P4-P6P7-P9P10-P12
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD7396/AD7397
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1998
3 V, Parallel Input
Dual 12-Bit /10-Bit DACs
FUNCTIONAL BLOCK DIAGRAM
DACA
REGISTER
12
INPUTA
REGISTER
DACB
REGISTER
12
INPUTB
REGISTER
AD7396
12-BIT
DACA
12-BIT
DACB
1
DATA
LDA
CS
A/B
DGND
RS SHDN
V
DD
V
OUTA
V
REF
V
OUTB
AGND
LDB
12
FEATURES
Micropower: 100 ␮A/DAC
0.1 ␮A Typical Power Shutdown
Single Supply +2.7 V to +5.5 V Operation
Compact 1.1 mm Height TSSOP 24-Lead Package
AD7396: 12-Bit Resolution
AD7397: 10-Bit Resolution
0.9 LSB Differential Nonlinearity Error
APPLICATIONS
Automotive Output Span Voltage
Portable Communications
Digitally Controlled Calibration
PC Peripherals
GENERAL DESCRIPTION
The AD7396/AD7397 series of dual, 12-bit and 10-bit voltage-
output digital-to-analog converters are designed to operate from
a single +3 V supply. Built using a CBCMOS process, these
monolithic DACs offer the user low cost and ease of use in
single supply +3 V systems. Operation is guaranteed over the
supply voltage range of +2.7 V to +5.5 V, making this device
ideal for battery operated applications.
A 12-bit wide data latch loads with a 45 ns write time allowing
interface to fast processors without wait states. The double
buffered input structure allows the user to load the input
registers one at a time, then a single load strobe tied to both
LDA+LDB inputs will simultaneously update both DAC out-
puts. LDA and LDB can also be independently activated to
immediately update their respective DAC registers. An address
input (A/B) decodes DACA or DACB when the chip select CS
input is strobed. Additionally, an asynchronous RS input sets
the output to zero-scale at power on or upon user demand.
Power shutdown to submicroamp levels is directly controlled by
the active low SHDN pin. While in the power shutdown state
register data can still be changed even though the output buffer
is in an open circuit state. Upon return to the normal operating
state the latest data loaded in the DAC register will establish the
output voltage.
Both parts are offered in the same pinout, allowing users to
select the amount of resolution appropriate for their applications
without circuit card changes.
The AD7396/AD7397 are specified for operation over the ex-
tended industrial (–40°C to +85°C) temperature range. The
AD7397AR is specified for the –40°C to +125°C automotive
temperature range. AD7396/AD7397s are available in plastic
DIP, and 24-lead SOIC packages. The AD7397ARU is avail-
able for ultracompact applications in a thin 1.1 mm height
TSSOP 24-lead package.
CODE – Decimal
1.0
0
DNL – LSB
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
512 1024 1536 2048 2560 3072 3584 4096
V
DD
= +3V
V
REF
= +2.5V
T
A
= +258C, +858C, –558C
SUPERIMPOSED
Figure 1. DNL vs. Digital Code at Temperature
–2–
REV. 0
AD7396/AD7397–SPECIFICATIONS
Parameter Symbol Conditions +3 V ⴞ 10% +5 V ⴞ 10% Units
STATIC PERFORMANCE
Resolution
1
N 12 12 Bits
Relative Accuracy
2
INL T
A
= +25°C ±1.75 ±1.75 LSB max
Relative Accuracy
2
INL T
A
= –40°C, +85°C ±2.0 ±2.0 LSB max
Differential Nonlinearity
2
DNL T
A
= +25°C, Monotonic ±0.9 ±0.9 LSB max
Differential Nonlinearity
2
DNL Monotonic ±1 ±1 LSB max
Zero-Scale Error V
ZSE
Data = 000
H
, T
A
= +25°C, +85°C 4.0 4.0 mV max
Zero-Scale Error V
ZSE
Data = 000
H
, T
A
= –40°C 8.0 8.0 mV max
Full-Scale Voltage Error V
FSE
T
A
= +25°C, +85°C, Data = FFF
H
±8 ±8mV max
Full-Scale Voltage Error V
FSE
T
A
= –40°C, Data = FFF
H
±20 ±20 mV max
Full-Scale Tempco
3
TCV
FS
–45 –45 ppm/°C typ
REFERENCE INPUT
V
REF
Range V
REF
0/V
DD
0/V
DD
V min/max
Input Resistance R
REF
2.5 2.5 MΩ typ
4
Input Capacitance
3
C
REF
55pF typ
ANALOG OUTPUT
Output Current (Source) I
OUT
Data = 800
H
, ∆V
OUT
= 5 LSB 1 1 mA typ
Output Current (Sink) I
OUT
Data = 800
H
, ∆V
OUT
= 5 LSB 3 3 mA typ
Capacitive Load
3
C
L
No Oscillation 100 100 pF typ
LOGIC INPUTS
Logic Input Low Voltage V
IL
0.5 0.8 V max
Logic Input High Voltage V
IH
V
DD
– 0.6 4.0 V min
Input Leakage Current I
IL
10 10 µA max
Input Capacitance
3
C
IL
10 10 pF max
INTERFACE TIMING
3, 5
Chip Select Write Width t
CS
45 35 ns min
DAC Select Setup t
AS
30 15 ns min
DAC Select Hold t
AH
0 0 ns min
Data Setup t
DS
30 15 ns min
Data Hold t
DH
20 10 ns min
Load Setup t
LS
20 20 ns min
Load Hold t
LH
10 10 ns min
Load Pulsewidth t
LDW
30 30 ns min
Reset Pulsewidth t
RSW
40 30 ns min
AC CHARACTERISTICS
Output Slew Rate SR Data = 000
H
to FFF
H
to 000
H
0.05 0.05 V/µs typ
Settling Time
6
t
S
To ±0.1% of Full Scale 70 60 µs typ
Shutdown Recovery Time t
SDR
90 80 µs typ
DAC Glitch Q Code 7FF
H
to 800
H
to 7FF
H
65 65 nV/s typ
Digital Feedthrough Q 15 15 nV/s typ
Feedthrough V
OUT
/V
REF
V
REF
= 1.5 V
DC
+1 V p-p
,
Data = 000
H
, f = 100 kHz –63 –63 dB typ
SUPPLY CHARACTERISTICS
Power Supply Range V
DD RANGE
DNL < ±1 LSB 2.7/5.5 2.7/5.5 V min/max
Positive Supply Current I
DD
V
IL
= 0 V, No Load 125/200 125/200 µA typ/max
Shutdown Supply Current I
DD_SD
SHDN = 0, V
IL
= 0 V, No Load 0.1/1.5 0.1/1.5 µA typ/max
Power Dissipation P
DISS
V
IL
= 0 V, No Load 600 1000 µW max
Power Supply Sensitivity PSS ∆V
DD
= ±5% 0.006 0.006 %/% max
NOTES
1
One LSB = V
REF
/4096 V for the 12-bit AD7396.
2
The first two codes (000
H
, 001
H
) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at +25°C.
5
All input control signals are specified with t
R
= t
F
= 2 ns (10% to 90% of +3 V) and timed from a voltage level of +1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
AD7396 12-BIT
ELECTRICAL CHARACTERISTICS
(@ V
REF IN
= +2.5 V, –40ⴗC < T
A
< +85ⴗC, unless otherwise noted)
–3–REV. 0
AD7396/AD7397
Parameter Symbol Conditions +3 V ⴞ 10% +5 V ⴞ 10% Units
STATIC PERFORMANCE
Resolution
1
N 10 10 Bits
Relative Accuracy
2
INL T
A
= +25°C ±1.75 ±1.75 LSB max
Relative Accuracy
2
INL T
A
= –40°C, +85°C, +125°C ±2.0 ±2.0 LSB max
Differential Nonlinearity
2
DNL Monotonic ±1 ±1LSB max
Zero-Scale Error V
ZSE
Data = 000
H
9.0 9.0 mV max
Full-Scale Voltage Error V
FSE
T
A
= +25°C, +85°C, +125°C, Data = 3FF
H
±42 ±42 mV max
Full-Scale Voltage Error V
FSE
T
A
= –40°C, Data = 3FF
H
±48 ±48 mV max
Full-Scale Tempco
3
TCV
FS
–45 –45 ppm/°C typ
REFERENCE INPUT
V
REF
Range V
REF
0/V
DD
0/V
DD
V min/max
Input Resistance R
REF
2.5 2.5 MΩ typ
4
Input Capacitance
3
C
REF
5 5 pF typ
ANALOG OUTPUT
Output Current (Source) I
OUT
Data = 200
H
, ∆V
OUT
= 5 LSB 1 1 mA typ
Output Current (Sink) I
OUT
Data = 200
H
, ∆V
OUT
= 5 LSB 3 3 mA typ
Capacitive Load
3
C
L
No Oscillation 100 100 pF typ
LOGIC INPUTS
Logic Input Low Voltage V
IL
0.5 0.8 V max
Logic Input High Voltage V
IH
V
DD
– 0.6 4.0 V min
Input Leakage Current I
IL
10 10 µA max
Input Capacitance
3
C
IL
10 10 pF max
INTERFACE TIMING
3, 5
Chip Select Write Width t
CS
45 35 ns min
DAC Select Setup t
AS
30 15 ns min
DAC Select Hold t
AH
0 0 ns min
Data Setup t
DS
30 15 ns min
Data Hold t
DH
20 10 ns min
Load Setup t
LS
20 20 ns min
Load Hold t
LH
10 10 ns min
Load Pulsewidth t
LDW
30 30 ns min
Reset Pulsewidth t
RSW
40 30 ns min
AC CHARACTERISTICS
Output Slew Rate SR Data = 000
H
to 3FF
H
to 000
H
0.05 0.05 V/µs typ
Settling Time
6
t
S
To ±0.1% of Full Scale 70 60 µs typ
Shutdown Recovery Time t
SDR
90 80 µs typ
DAC Glitch Q Code 7FF
H
to 800
H
to 7FF
H
65 65 nV/s typ
Digital Feedthrough Q 15 15 nV/s typ
Feedthrough V
OUT
/V
REF
V
REF
= 1.5 V
DC
+1 V p-p
,
Data = 000
H
, f = 100 kHz –63 –63 dB typ
SUPPLY CHARACTERISTICS
Power Supply Range V
DD RANGE
DNL < ±1 LSB 2.7/5.5 2.7/5.5 V min/max
Positive Supply Current I
DD
V
IL
= 0 V, No Load 125/200 125/200 µA typ/max
Shutdown Supply Current I
DD_SD
SHDN = 0, V
IL
= 0 V, No Load 0.1/1.5 0.1/1.5 µA typ/max
Power Dissipation P
DISS
V
IL
= 0 V, No Load 600 1000 µW max
Power Supply Sensitivity PSS ∆V
DD
= ±5% 0.006 0.006 %/% max
NOTES
1
One LSB = V
REF
/4096 V for the 10-bit AD7397.
2
The first two codes (000
H
, 001
H
) are excluded from the linearity error measurement.
3
These parameters are guaranteed by design and not subject to production testing.
4
Typicals represent average readings measured at +25°C.
5
All input control signals are specified with t
R
= t
F
= 2 ns (10% to 90% of +3 V) and timed from a voltage level of +1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
AD7397 10-BIT
ELECTRICAL CHARACTERISTICS
(@ V
REF IN
= +2.5 V, –40ⴗC < T
A
< +85ⴗC, unless otherwise noted)
P1-P3P4-P6P7-P9P10-P12

AD7396AR-REEL

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Manufacturer:
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Description:
Digital to Analog Converters - DAC Dual Parallel-Input 12-Bit
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