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AD7396AR-REEL

P1-P3P4-P6P7-P9P10-P12
AD7396/AD7397
–4–
REV. 0
Table I. Control Logic Truth
CS A/B LDA LDB RS SHDN Input Register DAC Register
L L HHHX Write to B Latched with Previous Data
L HHHHX Write to A Latched with Previous Data
L L H L H X Write to B B Transparent
L H L H H X Write to A A Transparent
H X L L H X Latched A and B Transparent
H X ^ ^ H X Latched Latched with New Data from Input REG
XXXXLX Reset to Zero Scale Reset to Zero Scale
HXXX^ X Latched to Zero Latched to Zero
^Denotes positive edge. The SHDN pin has no effect on the digital interface data loading; however, while in the SHDN state (SHDN = 0) the output amplifiers V
OUTA
and V
OUTB
exhibit an open circuit condition. Note, the LDx inputs are level-sensitive, the respective DAC registers are in a transparent state when LDx = “0.”
t
CSW
1 LSB
ERROR BAND
t
AS
t
AH
CS
A/B
t
DH
t
DS
t
LS
t
LH
t
LDW
t
RSW
t
S
t
S
LDA, LDB
RS
V
OUT
D0–D11
Figure 2. Timing Diagram
B REGISTER
1 OF 12
LATCHES
OF THE 2 INPUT
REGISTERS
TO DAC
REGISTERS
DBx
CS
A/B
RS
Figure 3. Digital Control Logic
AD7396/AD7397
–5–REV. 0
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7396/AD7397 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
V
REF
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
V
OUT
to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +2 V
I
OUT
Short Circuit to GND . . . . . . . . . . . . . . . . . . . . +50 mA
Package Power Dissipation . . . . . . . . . . . . . (T
J
max – T
A
)/θ
JA
Thermal Resistance θ
JA
24-Lead Plastic DIP Package (N-24) . . . . . . . . . . +63°C/W
24-Lead SOIC Package (R-24) . . . . . . . . . . . . . . . +70°C/W
24-Lead Thin Shrink Surface Mount (RU-24) . . +143°C/W
ORDERING GUIDE
Res Temperature Package Package
Model (LSB) Ranges Descriptions Options
AD7396AN 12 –40°C to +85°C 24-Lead P-DIP N-24
AD7396AR 12 –40°C to +85°C 24-Lead SOIC R-24
AD7397AN 10 –40°C to +125°C 24-Lead P-DIP N-24
AD7397AR 10 –40°C to +125°C 24-Lead SOIC R-24
AD7397ARU 10 –40°C to +85°C 24-Lead Thin Shrink Small Outline Package (TSSOP) RU-24
The AD7396/AD7397 contains 1365 transistors. The die size measures 89 mil × 106 mil = 9434 sq mil.
Maximum Junction Temperature (T
J
max) . . . . . . . . .+150°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
AD7397AN, AD7397AR Only . . . . . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature
␣ ␣ N-24 (Soldering, 10 sec) . . . . . . . . . . . . . . . . . . . . . .+300°C
␣ ␣ R-24 (Vapor Phase, 60 sec) . . . . . . . . . . . . . . . . . . . .+215°C
␣ ␣ RU-24 (Infrared, 15 sec) . . . . . . . . . . . . . . . . . . . . . .+224°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
AD7396/AD7397
–6–
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin No. Name
1V
OUTA
DAC A Voltage Output.
2 AGND Analog Ground.
3 DGND Digital Ground.
4 LDA Load DAC A Register Strobe. Transfers input register data to the DAC A register. Active
low inputs, Level sensitive latch. May be connected together with LDB to double-buffer load
both DAC registers simultaneously.
5 SHDN Power Shutdown Active Low Input. DAC register contents are saved as long as power stays
on the V
DD
pin.
6 RS Resets Input and DAC Register to Zero Condition. Asynchronous active low input.
7–18 D0–D11 Twelve Parallel Input Data Bits. D11 = MSB Pin 18, D0 = LSB Pin 7, AD7396.
7, 8 NC No Connect Pins 7 and 8 On the AD7397 Only.
9–18 D0–D9 Ten Parallel Input Data Bits. D9 = MSB Pin 18, D0 = LSB Pin 9, AD7397 Only.
19 CS Chip Select Latch Enable, Active Low.
20 A/B DAC Input Register Address Select DACA = 1 or DACB = 0.
21 LDB Load DAC B Register Strobe. Transfers input register data to the DAC B register. Active low
inputs, Level sensitive latch. May be connected together with LDA to double-buffer load
both DAC registers simultaneously.
22 V
DD
Positive Power Supply Input. Specified range of operation +2.7 V to +5.5 V.
23 V
REF
DAC Reference Input Pin. Establishes DAC full-scale voltage.
24 V
OUTB
DAC B Voltage Output.
PIN CONFIGURATIONS
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7396
D5
D4
D3
D2
D1
V
OUTA
AGND
DGND
LDA
D0
RS
SHDN
D6
D7
D8
D9
D10
V
OUTB
V
REF
V
DD
LDB
D11
CS
A/B
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7397
D3
D2
D1
D0
NC
V
OUTA
AGND
DGND
LDA
NC
RS
SHDN
D4
D5
D6
D7
D8
V
OUTB
V
REF
V
DD
LDB
D9
CS
A/B
NC = NO CONNECT
P1-P3P4-P6P7-P9P10-P12

AD7396AR-REEL

Mfr. #:
Buy AD7396AR-REEL
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Dual Parallel-Input 12-Bit
Lifecycle:
New from this manufacturer.
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