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LTC4280CUFD#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
LTC4280
19
4280f
APPLICATIONS INFORMATION
For a start-up time of 4ms with a 2x safety margin we
choose:
C
t
ms μF
C
ms
ms
TIMER
STARTUP
TIMER
=
=
2
12 3
8
12 3
•
./
./
μμF
μF≅ 068.
For an overcurrent fault fi lter time of 5ms we choose:
C
F
= t
FILTER
/123ms/µF ≅ 47nF
The UV and OV resistor string values can be solved in the
following method. First pick R3 based on I
STRING
being
1.235V/R3 at the edge of the OV rising threshold, where
I
STRING
> 40µA. Then solve the following equations:
R2 =
V
V
•R3•
UV
OV
OV(OFF)
UV(ON)
TH(RISING)
T
HH(FALLING)
UV(ON)
TH(RI
–R3
R1 =
V
UV
•( )RR32+
SSING)
––RR32
In our case we choose R3 to be 3.4k to give a resistor
string current below 100µA. Then solving the equations
results in R2 = 1.16k and R1 = 34.6k.
The FB divider is solved by picking R8 and solving for R7,
choosing 3.57k for R8 we get:
R7 =
V
FB
PWRGD(UP)
TH(RISING)
•
–
R
R
8
8
resulting in R7 = 30k.
A 0.1µF capacitor, C
F
, is placed on the UV pin to prevent
supply glitches from turning off the GATE via UV or OV.
The address is set with the help of Table 1, which indicates
binary address 1010011 corresponds to address 19.
Address 19 is set by setting ADR2 high, ADR1 open and
ADR0 high.
Next the value of R5 and R6 are chosen to be the default
values 10Ω and 15k as discussed previously.
UV
OV
FILTER
GND
ON
EN
SDAO
FB
GPIO
INTV
CC
TIMER
ADIN
ADR2
ADR1
V
DD
SENSE
+
SENSE
–
GATE
SOURCE
SDAI
SCL
ALERT
NC
ADR0
R2
R3
C
F
Z1
R1
SENSE RESISTOR R
S
C3
LTC4280UFD
R8
I
LOAD
4280 F05
I
LOAD
Figure 5. Recommended Layout
In addition a 0.1µF ceramic bypass capacitor is placed on
the INTV
CC
pin.
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
is required. The minimum trace width for 1oz copper
foil is 0.02" per amp to make sure the trace stays at a
reasonable temperature. Using 0.03" per amp or wider
is recommended. Note that 1oz copper exhibits a sheet
resistance of about 530µΩ/
®. Small resistances add up
quickly in high current applications. To improve noise
immunity, put the resistive dividers to the UV, OV and FB
pins close to the device and keep traces to V
DD
and GND
short. It is also important to put the bypass capacitor for
the INTV
CC
pin, C3, as close as possible between INTV
CC
and GND. A 0.1µF capacitor from the UV pin (and OV pin
through resistor R2) to GND also helps reject supply noise.
Figure 4 shows a layout that addresses these issues. Note
that a surge suppressor, Z1, is placed between supply and
ground using wide traces.
LTC4280
20
4280f
APPLICATIONS INFORMATION
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS R/W ACK DATA ACK DATA ACK
1 - 7 8 9
4280 F06
a6 - a0 b7 - b0 b7 - b0
1 - 7 8 9 1 - 7 8 9
P
S
Figure 6. Data Transfer Over I
2
C or SMBus
Digital Interface
The LTC4280 communicates with a bus master using a
2-wire interface compatible with I
2
C Bus and SMBus, an
I
2
C extension for low power devices.
The LTC4280 is a read-write slave device and supports
SMBus bus Read Byte, Write Byte, Read Word and Write
Word commands. The second word in a Read Word
command is identical to the fi rst word. The second word
in a Write Word command is ignored. Data formats for
these commands are shown in Figures 6 to 11.
START and STOP Conditions
When the bus is idle, both SCL and SDA are high. A bus
master signals the beginning of a transmission with a start
condition by transitioning SDA from high to low while SCL
is high, as shown in Figure 6. When the master has fi nished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
I
2
C Device Addressing
Twenty-seven distinct bus addresses are available using
three 3-state address pins, ADR0-ADR2. Table 1 shows
the correspondence between pin states and addresses.
Note that address bits B7 and B6 are internally confi gured
to 10. In addition, the LTC4280 responds to two special
addresses. Address (1011 111) is a mass write address
that writes to all LTC4280s, regardless of their individual
address settings. Mass write can be disabled by setting
register A4 to zero. Address (0001 100) is the SMBus Alert
Response Address. If the LTC4280 is pulling low on the
ALERT pin, it acknowledges this address by broadcasting
its address and releasing the ALERT pin.
Acknowledge
The acknowledge signal is used in handshaking between
transmitter and receiver to indicate that the last byte of
data was received. The transmitter always releases the
SDA line during the acknowledge clock pulse. When the
slave is the receiver, it pulls down the SDA line so that it
LTC4280
21
4280f
APPLICATIONS INFORMATION
remains LOW during this pulse to acknowledge receipt
of the data. If the slave fails to acknowledge by leaving
SDA high, then the master may abort the transmission by
generating a STOP condition. When the master is receiving
data from the slave, the master pulls down the SDA line
during the clock pulse to indicate receipt of the data. After
the last byte has been received the master leaves the SDA
line HIGH (not acknowledge) and issues a stop condition
to terminate the transmission.
Write Protocol
The master begins communication with a START condition
followed by the seven bit slave address and the R/W bit
set to zero, as shown in Figure 7. The addressed LTC4280
acknowledges this and then the master sends a command
byte which indicates which internal register the master
wishes to write. The LTC4280 acknowledges this and
then latches the lower three bits of the command byte
into its internal Register Address pointer. The master then
delivers the data byte and the LTC4280 acknowledges
once more and latches the data into its control register.
The transmission is ended when the master sends a STOP
condition. If the master continues sending a second data
byte, as in a Write Word command, the second data byte
is acknowledged by the LTC4280 but ignored, as shown
in Figure 8.
Read Protocol
The master begins a read operation with a START condition
followed by the seven bit slave address and the R/W bit
set to zero, as shown in Figure 9. The addressed LTC4280
acknowledges this and then the master sends a command
byte which indicates which internal register the master
wishes to read. The LTC4280 acknowledges this and then
latches the lower three bits of the command byte into its
internal Register Address pointer. The master then sends
a repeated START condition followed by the same seven
bit address with the R/W bit now set to one. The LTC4280
acknowledges and send the contents of the requested
register. The transmission is ended when the master
sends a STOP condition. If the master acknowledges
the transmitted data byte, as in a Read Word command,
Figure 10, the LTC4280 repeats the requested register as
the second data byte.
Alert Response Protocol
When any of the fault bits in FAULT register D are set, an
optional bus alert is generated if the appropriate bit in
the ALERT register B is also set. If an alert is enabled, the
corresponding fault causes the ALERT pin to pull low. After
the bus master controller broadcasts the Alert Response
Address, the LTC4280 responds with its address on the
SDA line and then release ALERT as shown in Figure 11.
The ALERT line is also released if the device is addressed
by the bus master. The ALERT signal is not pulled low
again until the FAULT register indicates a different fault
has occurred or the original fault is cleared and it occurs
again. Note that this means repeated or continuing faults
do not generate alerts until the associated FAULT register
bit has been cleared.
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LTC4280CUFD#PBF

Mfr. #:
Buy LTC4280CUFD#PBF
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Hot Swap Contr. w/ADC and I2C, 3 GPIOs
Lifecycle:
New from this manufacturer.
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