DAC8043
Rev. E | Page 11 of 16
To further ensure accuracy across the full temperature range,
permanently on MOS switches were included in series with
the feedback resistor and the terminating resistor of the R-2R
ladder. The simplified DAC circuit, Figure 13, shows the location
of the series switches. These series switches are equivalently
scaled to two times Switch S1 (MSB) and to Switch S12 (LSB),
respectively, to maintain constant relative voltage drops with
varying temperature. During any testing of the resistor ladder
or R
FEEDBACK
(such as incoming inspection), V
DD
must be present
to turn on these series switches.
00271-013
20kΩ
20kΩ 20kΩ
GND
I
OUT
R
FEEDBACK
S12S3
20kΩ
S2
20kΩ
S1
V
REF
10kΩ 10kΩ
*THESE SWITCHES PERMANENTLY ON.
10kΩ
10kΩ
BIT 1 (MSB) BIT 2
DIGITAL INPUTS
(SWITCHES SHOWN FOR DIGITAL INPUTS (HIGH))
BIT 3 BIT 12 (LSB)
*
*
Figure 13. Simplified DAC Circuit
EQUIVALENT CIRCUIT ANALYSIS
Figure 14 shows an equivalent analog circuit for the DAC8043.
The (D × V
REF
)/R current source is code dependent and is the
current generated by the DAC. The current source, I
LKG
, consists
of surface and junction leakages and doubles approximately
every 10°C. C
OUT
is the output capacitance; it is the result of
the N-channel MOS switches and varies from 80 pF to 110 pF,
depending on the digital input code. R
O
is the equivalent out-
put resistance that also varies with digital input code. R is the
nominal R-2R resistor ladder resistance.
00271-014
R
C
OUT
R
FB
I
OUT
V
REF
GND
I
LKG
D × V
REF
R
R
R
Figure 14. Equivalent Analog Circuit
DYNAMIC PERFORMANCE
Output Impedance
The output resistance of the DAC8043, as in the case of the
output capacitance, varies with the digital input code. This
resistance, looking back into the I
OUT
terminal, may be between
10 kΩ (the feedback resistor alone when all digital inputs are low)
and 7.5 kΩ (the feedback resistor in parallel with approximately
30 kΩ of the R-2R ladder network resistance when any single bit
logic is high). Static accuracy and dynamic performance will be
affected by these variations. This variation is best illustrated by
using the circuit of Figure 15 and the following equation:
+=
O
FB
OSERROR
R
R
VV 1
where:
R
O
is a function of the digital code and
= 10 kΩ for more than four bits of Logic 1.
= 30 kΩ for any single bit of Logic 1.
Therefore, the offset gain varies as follows:
At Code 0011 1111 1111,
OSOS
1
ERROR
VVV 2
kΩ10
kΩ10
1 =
+=
At Code 0100 0000 0000,
OSOS
2
ERROR
VVV 3/4
kΩ30
kΩ10
1 =
+=
The error difference is 2/3 V
OS
.
Because one LSB has a weight (for V
REF
= 10 V) of 2.4 mV for
the DAC8043, it is clearly important that V
OS
be minimized,
either by using the amplifier’s nulling pins or an external nulling
network or by selecting an amplifier with inherently low V
OS
.
Amplifiers with sufficiently low V
OS
include OP77, OP07, OP27,
and OP42.
00271-015
R
FB
V
REF
2R 2R 2R
ETC
RRR
OP77
V
OS
Figure 15. Simplified Circuit
The gain and phase stability of the output amplifier, board
layout, and power supply decoupling all affect the dynamic
performance. The use of a small compensation capacitor may
be required when high speed operational amplifiers are used. It
may be connected across the feedback resistor of the amplifier
to provide the necessary phase compensation to critically damp
the output. The output capacitance of the DAC8043 and the R
FB
resistor form a pole that must be outside the amplifier’s unity
gain crossover frequency.
The considerations when using high speed amplifiers are:
1. Phase compensation (see Figure 16 and Figure 17).
2. Power supply decoupling at the device socket and the use
of proper grounding techniques.
