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LTC2933CGN#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
LTC2933
13
2933fa
For more information www.linear.com/LTC2933
DETAILED COMMAND REGISTER DESCRIPTIONS
WRITE_PROTECT (Command Byte 0x00)
The WRITE_PROTECT command provides the ability to
prevent any write operations into the volatile memory, if
WRITE_LOCK = 1. KEY may be changed when WRITE_LOCK
= 0, or in the same command that sets WRITE_LOCK = 1.
When locked, WRITE_LOCK can only be written to 0 if
KEY matches the existing value in memory. For effective
protection against false writes, KEY should contain at
least one bit set to 1.
Writes to supported commands are ignored when
WRITE_LOCK = 1. All commands may be read regardless
of the WRITE_LOCK bit setting.
operaTion
WRITE_PROTECT Data Contents
BIT(S) SYMBOL PURPOSE
b[15:2] KEY Must match against programmed combination in order to deactivate write lock.
Factory default 10_1010_1010_1010b (0x2AAA).
b[1]
Reserved Ignore
b[0] WRITE_LOCK 0: Unlocked. Writes to volatile memory are permitted.
1: Locked. Writing to volatile memory is not permitted. To unlock, set WRITE_LOCK = 0 with the
appropriate key.
Factor
y default 0.
LTC2933
14
2933fa
For more information www.linear.com/LTC2933
operaTion
GPI_CONFIG Data Contents
BIT(S) SYMBOL OPERATION
b[15] Reserved Ignore
b[14] GPI2_MR_RESPONSE Effective only if the input GPI2 is MR configured.
0: Disable CLEAR_HISTORY response.
1: Enable CLEAR_HISTORY response on falling edge of GPI2.
Factory default 0.
b
[13:11]
GPI2_CONFIG 000b: Manual Reset (MR) active low, 15µA pull-up.
001b: Reserved.
010b: Margin (MARG) active low, 15µA pull-up. Overvoltage and undervoltage faults are inhibited.
011b: UV Disable (UVDIS) active low, 15µA pull-up. Undervoltage faults are inhibited.
100b: and 101b: Auxiliary Comparator (AUXC) positive input on GPI2.
110b: and 111b: Auxiliary Comparator (AUXC) negative input on GPI2.
Factory default 010b.
b
[10]
MAP_GPI2_TO_GPIO3 0: GPI2 input is not mapped to GPIO3.
1: GPI2 input is mapped to GPIO3 if configured as MR or AUXC.
Factory default 0.
b[9]
MAP_GPI2_TO_GPIO2 0: GPI2 input is not mapped to GPIO2.
1: GPI2 input is mapped to GPIO2 if configured as MR or AUXC.
Factory default 0.
b[8]
MAP_GPI2_TO_GPIO1 0: GPI2 input is not mapped to GPIO1.
1: GPI2 input is mapped to GPIO1 if configured as MR or AUXC.
Factory default 0.
b[7]
Reserved Ignore
b[6] GPI1_MR_RESPONSE Effective only if the input GPI1 is MR configured.
0: Disable CLEAR_HISTORY response.
1: Enable CLEAR_HISTORY response on falling edge of GPI1.
Factory default 0.
b[5:3]
GPI1_CONFIG 000b: Manual Reset (MR) active low, 15µA pull-up.
001b: Reserved.
010b: Margin (MARG) active low, 15µA pull-up. Overvoltage and undervoltage faults are inhibited.
011b: UV Disable (UVDIS) active low, 15µA pull-up. Undervoltage faults are inhibited.
100b: and 101b: Auxiliary Comparator (AUXC) positive input on GPI1.
110b: and 111b: Auxiliary Comparator (AUXC) negative input on GPI1.
Factory default 000b.
b
[2]
MAP_GPI1_TO_GPIO3 0: GPI1 input is not mapped to GPIO3.
1: GPI1 input is mapped to GPIO3 if configured as MR or AUXC.
Factory default 0.
b[1]
MAP_GPI1_TO_GPIO2 0: GPI1 input is not mapped to GPIO2.
1: GPI1 input is mapped to GPIO2 if configured as MR or AUXC.
Factory default 0.
b[0]
MAP_GPI1_TO_GPIO1 0: GPI1 input is not mapped to GPIO1.
1: GPI1 input is mapped to GPIO1 if configured as MR or AUXC.
Factory default 0.
GPI_CONFIG (Command Byte 0x01)
The GPI_CONFIG command configures internal response
to a manual reset, sets each GPI function, and option-
ally maps GPI pins configured as Manual Reset (MR) or
Auxiliary Comparator (AUXC) to one or more GPIO pins.
LTC2933
15
2933fa
For more information www.linear.com/LTC2933
GPIO1_CONFIG (Command Byte 0x02)
The GPIO1_CONFIG command configures the GPIO1
mapping, delay-on-release time, output type, and polarity.
If GPIO1_TYPE_AND_POLARITY is configured as ALERT
(100b or 111b), the output is latched and cleared after the
operaTion
GPIO1_CONFIG Data Contents
BIT(S) SYMBOL OPERATION
b[15:8] Reserved Ignore
b[7]
MAP_GPIO1_TO_GPIO3
0: GPIO1 input is not mapped to GPIO3.
1: GPIO1 input is mapped to GPIO3.
Factory default 0.
b[6]
MAP_GPIO1_TO_GPIO2
0: GPIO1 input is not mapped to GPIO2.
1: GPIO1 input is mapped to GPIO2.
Factor
y default 0.
b[5:3]
GPIO1_DELAY_ON_RELEASE 000b: Delay selected is 0.
001b: Delay selected is 1.6ms.
010b: Delay selected is 6.4ms.
011b: Delay selected is 26ms.
100b: Delay selected is 51ms.
101b: Delay selected is 205ms.
110b: Delay selected is 410ms.
111b: Delay selected is 1.64s.
Factory default 101b (205ms).
b
[2:0]
GPIO1_TYPE_AND_POLARITY 000b: Active H input.
001b: Active L input.
010b: Active H open-drain output.
011b: Active L open-drain output.
100b: Active L open-drain ALERT output.
101b: Active H, weak pull-up output.
110b: Active L, weak pull-up output.
111b: Active L, weak pull-up ALERT output.
Factory default 011b (Active L open-drain output).
LTC2933 acknowledges the alert response address (see
SMBus protocol), HISTORY_WORD is read, or a CLEAR_
HISTORY command is received. Only one GPIO
n
pin should
be configured as ALERT. GPIO
n
_DELAY_ON_RELEASE
does not apply to a GPIO
n
pin configured as ALERT.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34

LTC2933CGN#TRPBF

Mfr. #:
Buy LTC2933CGN#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Supervisory Circuits Programmable Hex Voltage Supervisor (w/ High Voltage Input)
Lifecycle:
New from this manufacturer.
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