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NB7LQ572MNG

P1-P3P4-P6P7-P9P10-P12
NB7LQ572
http://onsemi.com
7
Figure 4. Typical Output Waveform at 2 GHz
(V
INPP
= 175 mV, V
CC
= 2.38 V)
Figure 5. Typical Output Waveform at 5 GHz
(V
INPP
= 175 mV, V
CC
= 2.38 V)
126 mV/DIV 95 ps/DIV 126 mV/DIV 37.5 ps/DIV
Q
NB7LQ572
Equalizer Receiver
Digital
Oscilloscope
Q
FR4 = 12” Backplane
50W
50W
Signal Generator
NB7LQ572 INPUT
NB7LQ572 INPUT NB7LQ572 OUTPUT
NB7LQ572 OUTPUT
26 mV/div 56 ps/div 126 mV/div 56 ps/div
26 mV/div 25.5 ps/div 126 mV/div 25.5 ps/div
Figure 6. Typical NB7LQ572 Equalizer Application and Interconnect; Eye Diagrams with PRBS23 Pattern at 3 Gbps
and 6.5 Gbps after 12 inches of FR4
Typical Input Waveform at 3 Gbps with PRBS23
after 12 in FR4 (V
INPP
= 175 mV, V
CC
= 2.38 V)
Typical Output Waveform at 3 Gbps with PRBS23
after 12 in FR4 (V
INPP
= 175 mV, V
CC
= 2.38 V)
Typical Input Waveform at 6.5 Gbps with PRBS23
after 12 in FR4 (V
INPP
= 175 mV, V
CC
= 2.38 V)
Typical Output Waveform at 6.5 Gbps with PRBS23
after 12 in FR4 (V
INPP
= 175 mV, V
CC
= 2.38 V)
NB7LQ572
http://onsemi.com
8
Figure 7. Typical Phase Noise Plot at f
carrier
= 1 GHz
The phase noise plot was captured using an Agilent E5052A which shows additive phase noise of the NB7LQ572 at 1 GHz, an operat-
ing voltage of 2.5 V at room temperature. The RMS Phase Jitter contributed by the device (integrated between 12 kHz and 20 MHz) is
35 fs. The input source used for the phase noise measurement is an Agilent E8663B.
NB7LQ572
http://onsemi.com
9
Figure 8. Input Structure
Figure 9. Differential Input Driven Single−Ended
Figure 10. V
th
Diagram Figure 11. Differential Inputs Driven Differentially
Figure 12. Differential Inputs Driven Differentially
Figure 13. VCMR Diagram
Figure 14. AC Reference Measurement
V
IHD
V
ILD
V
ID
= |V
IHD(IN)
− V
ILD(IN)
|
IN
IN
IN
V
th
IN
IN
IN
IN
IN
Q
Q
t
PLH
t
PHL
V
INPP
= V
IH
(IN) − V
IL
(IN)
V
OUTPP
= V
OH
(Q) − V
OL
(Q)
50 W
50 W
INx
VTx
INx
V
CC
GND
V
thmin
V
thmax
Vth
IN
V
IHmax
V
ILmax
V
IH
V
th
V
IL
V
IHmin
V
ILmin
V
CC
GND
V
CMmin
V
CMmax
V
CMR
IN
IN
V
IHDmax
V
ILDmax
V
ID
= V
IHD
− V
ILD
V
IHDtyp
V
ILDtyp
V
IHDmin
V
ILDmin
V
th
V
IH
V
IL
Figure 15. SELx to Qx Timing Diagram
tpd tpd
V
CC
/ 2 V
CC
/ 2
SELx
Q
Q
V
CC
P1-P3P4-P6P7-P9P10-P12

NB7LQ572MNG

Mfr. #:
Buy NB7LQ572MNG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 7 GHz160 ps3.6V 3V
Lifecycle:
New from this manufacturer.
Delivery:
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