Nexperia
PRMD13
50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)
PRMD13 All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet 25 July 2017 3 / 16
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Per transistor, for the PNP transistor with negative polarity
V
CBO
collector-base voltage open emitter - 50 V
V
CEO
collector-emitter voltage open base - 50 V
V
EBO
emitter-base voltage open collector - 5 V
negative -5 - VV
I
input voltage
positive - 30 V
I
O
output current - 100 mA
P
tot
total power dissipation T
amb
≤ 25 °C [1] - 325 mW
Per device
P
tot
total power dissipation T
amb
≤ 25 °C [1] - 480 mW
T
j
junction temperature - 150 °C
T
amb
ambient temperature -55 150 °C
T
stg
storage temperature -65 150 °C
[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint.
-75 17512525 75-25
aaa-024487
200
300
100
400
500
P
tot
(mW)
0
FR4 PCB, standard footprint
Fig. 1. Per device: Power derating curve