R1LP0408D Series
R10DS0104EJ0200 Rev.2.00 Page 11 of
11
2012.5.30
Low Vcc Data Retention Characteristics
Parameter Symbol Min. Typ. Max. Unit Test conditions
*3
V
CC
for data retention V
DR
2.0 ─ 5.5 V
Vin ≥ 0V,
CS# ≥ Vcc-0.2V
─ 0.8
*1
2.5 μA ~+25°C
─ 1
*2
3 μA ~+40°C
─ ─ 8 μA ~+70°C
Data retention current I
CCDR
─ ─ 10 μA ~+85°C
Vcc=3.0V, Vin ≥ 0V,
CS# ≥ Vcc-0.2V
Chip deselect time to data retention t
CDR
0 ─ ─ ns
Operation recovery time t
R
5 ─ ─ ms
See retention waveform.
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.
2. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=40ºC), and not 100% tested.
3. CS# controls address buffer, WE# buffer, OE# buffer and Din buffer. If data retention mode, Vin levels
(address, WE#, OE#, I/O) can be in the high impedance state.
Low Vcc Data Retention Timing Waveforms
CS#
Vcc
CS# Controlled
t
CDR
t
R
4.5V 4.5V
2.2V 2.2V
DR
CS# ≥ Vcc - 0.2V
