R1LP0408D Series
R10DS0104EJ0200 Rev.2.00 Page 7 of
11
2012.5.30
Read Cycle
R1LP0408DS*-5S* R1LP0408DS*-7S*
Parameter Symbol
Min. Max. Min. Max.
Unit Note
Read cycle time t
RC
55 ─ 70 ─ ns
Address access time t
AA
─ 55 ─ 70 ns
Chip select access time t
ACS
─ 55 ─ 70 ns
Output enable to output valid t
OE
─ 25 ─ 35 ns
Chip select to output in low-Z t
CLZ
10 ─ 10 ─ ns 2
Output enable to output in low-Z t
OLZ
5 ─ 5 ─ ns 2
Chip deselect to output in high-Z t
CHZ
0 20 0 25 ns 1,2
Output disable to output in high-Z t
OHZ
0 20 0 25 ns 1,2
Output hold from address change t
OH
10 ─ 10 ─ ns
Write Cycle
R1LP0408DS*-5S* R1LP0408DS*-7S*
Parameter Symbol
Min. Max. Min. Max.
Unit Note
Write cycle time t
WC
55 ─ 70 ─ ns
Chip select to end of write t
CW
50 ─ 60 ─ ns 4
Address setup time t
AS
0 ─ 0 ─ ns 5
Address valid to end of write t
AW
50 ─ 60 ─ ns
Write pulse width t
WP
40 ─ 50 ─ ns 3,12
Write recovery time t
WR
0 ─ 0 ─ ns 6
Write to output in high-Z t
WHZ
0 20 0 25 ns 1,2,7
Data to write time overlap t
DW
25 ─ 30 ─ ns
Data hold from write time t
DH
0 ─ 0 ─ ns
Output enable from end of write t
OW
5 ─ 5 ─ ns 2
Output disable to output in high-Z t
OHZ
0 20 0 25 ns 1,2,7
Note 1. t
CHZ
, t
OHZ
and t
WHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not
referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (t
WP
) of a low CS# and a low WE#.
A write begins at the later transition of CS# going low or WE# going low.
A write ends at the earlier transition of CS# going high or WE# going high.
t
WP
is measured from the beginning of write to the end of write.
4. t
CW
is measured from CS# going low to end of write.
5. t
AS
is measured the address valid to the beginning of write.
6. t
WR
is measured from the earlier of WE# or CS# going high to the end of write cycle.
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to the
outputs must not be applied.
8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE# transition, the
output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10. Dout is the read data of next address.
11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of the opposite
phase to the outputs must not be applied to them.
12. In the write cycle with OE# low fixed, t
WP
must satisfy the following equation to avoid a problem of data bus
contention.
t
WP
≥ t
DW
min + t
WHZ
max
