MAX16824/MAX16825
High-Voltage, Three-Channel Linear
High-Brightness LED Drivers
6
Maxim Integrated
Pin Description
PIN
MAX16824 MAX16825
NAME FUNCTION
1 1 OUT1
Channel 1 LED Driver Output. OUT1 is an open-drain, constant-current-sinking output
rated to 36V.
2 2 CS1
Channel 1 Sense Amplifier Negative Input. Connect a current-sense resistor between
CS1 and GND to program the output current level for channel 1.
3 3 IN Positive Input Supply. Bypass with a 0.1µF (min) capacitor to GND.
4 4 REG +5V-Regulated Output. Connect a 1µF capacitor from REG to GND.
5, 6, 10, 14 5, 14 N.C. No Connection. Must be left unconnected.
7 — PWM1
Dimming Input 1. PWM1 is a dimming input for channel 1. A logic-low turns off OUT1 and
a logic-high turns on OUT1.
8 — PWM2
Dimming Input 2. PWM2 is a dimming input for channel 2. A logic-low turns off OUT2 and
a logic-high turns on OUT2.
9 — PWM3
Dimming Input 3. PWM3 is a dimming input for channel 3. A logic-low turns off OUT3 and
a logic-high turns on OUT3.
11 11 GND Ground
12 12 OUT3
Channel 3 LED Driver Output. OUT3 is an open-drain, constant-current-sinking output
rated to 36V.
13 13 CS3
Channel 3 Sense Amplifier Negative Input. Connect a current-sense resistor between
CS3 and GND to program the output current level for channel 3.
15 15 CS2
Channel 2 Sense Amplifier Negative Input. Connect a current-sense resistor between
CS2 and GND to program the output current level for channel 2.
16 16 OUT2
Channel 2 LED Driver Output. OUT2 is an open-drain, constant-current-sinking output
rated to 36V.
—7DIN
Serial-Data Input. Data is loaded into the internal 3-bit shift register on the rising edge of
CLK.
—8LE
Latch-Enable Input. Data loaded transparently from the internal shift register to the
output latch while LE is high. Data is latched into the output latch on the LE’s falling edge
and retained while LE is low.
—9OE
Output Enable Input. Drive OE high to place all outputs into a high-impedance mode
without altering the contents of the output latches. Drive OE low to force all outputs to
follow the state of the output latches.
—10DOUT
Serial-Data Output. Data is clocked out of the internal 3-bit shift register to DOUT on the
rising edge of CLK. DOUT is a replica of the shift register’s last bit.
— 6 CLK Clock Input
——EP
Exposed Pad. Connect EP to a large-area ground plane for effective power dissipation.
Do not use as the IC ground connection.