OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

MT9M021IA3XTMZH-GEVB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
MT9M021, MT9M031
www.onsemi.com
10
ELECTRICAL SPECIFICATIONS
Unless otherwise stated, the following specifications
apply to the following conditions:
V
DD
= 1.8 V –0.10/+0.15;
V
DD
_IO = V
DD
_PLL = V
AA
= V
AA
_PIX = 2.8 V ±0.3 V;
V
DD
_SLVS = 0.4 V –0.1/+0.2;
T
A
= −30°C to +70°C;
Output Load = 10 pF;
PIXCLK Frequency = 74.25 MHz;
HiSPi off.
Two-Wire Serial Register Interface
The electrical characteristics of the two-wire serial
register interface (S
CLK
, S
DATA
) are shown in Figure 6 and
Table 5.
Figure 6. Two-Wire Serial Bus Timing Parameters
S
DATA
S
CLK
S Sr P S
t
f
t
r
t
f
t
r
t
SU;DAT
t
HD;STA
t
SU;STO
t
SU;STA
t
BUF
t
HD;DAT
t
HIGH
t
LOW
t
HD;STA
NOTE: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued.
Table 5. TWO-WIRE SERIAL BUS CHARACTERISTICS
(f
EXTCLK
= 27 MHz; V
DD
= 1.8 V; V
DD
_IO = 2.8 V; V
AA
= 2.8 V; V
AA
_PIX = 2.8 V; V
DD
_PLL = 2.8 V; T
A
= 25°C)
Parameter
Symbol
Standard Mode Fast-Mode
Unit
Min Max Min Max
S
CLK
Clock Frequency f
SCL
0 100 0 400 kHz
Hold Time (Repeated) START
Condition
t
HD;STA
4.0 − 0.6 −
ms
LOW Period of the S
CLK
Clock t
LOW
4.7 − 1.3 −
ms
HIGH Period of the S
CLK
Clock t
HIGH
4.0 − 0.6 −
ms
Set-up Time for a Repeated
START Condition
t
SU;STA
4.7 − 0.6 −
ms
Data Hold Time t
HD;DAT
0 (Note 4) 3.45 (Note 5) 0 (Note 6) 0.9 (Note 5)
ms
Data Set-up Time t
SU;DAT
250 − 100 (Note 6) − ns
Rise Time of both S
DATA
and
S
CLK
Signals
t
r
− 1000 20 + 0.1Cb
(Note 7)
300 ns
Fall Time of both S
DATA
and S
CLK
Signals
t
f
− 300 20 + 0.1Cb
(Note 7)
300 ns
Set-up Time for STOP Condition t
SU;STO
4.0 − 0.6 −
ms
Bus Free Time between a STOP
and START Condition
t
BUF
4.7 − 1.3 −
ms
Capacitive Load for each Bus Line Cb − 400 − 400 pF
Serial Interface Input Pin
Capacitance
CIN_SI − 3.3 − 3.3 pF
MT9M021, MT9M031
www.onsemi.com
11
Table 5. TWO-WIRE SERIAL BUS CHARACTERISTICS (continued)
(f
EXTCLK
= 27 MHz; V
DD
= 1.8 V; V
DD
_IO = 2.8 V; V
AA
= 2.8 V; V
AA
_PIX = 2.8 V; V
DD
_PLL = 2.8 V; T
A
= 25°C)
Parameter Unit
Fast-ModeStandard Mode
Symbol
Parameter Unit
MaxMinMaxMin
Symbol
S
DATA
Max Load Capacitance CLOAD_SD − 30 − 30 pF
S
DATA
Pull-up Resistor RSD 1.5 4.7 1.5 4.7
kW
1. This table is based on I
2
C standard (v2.1 January 2000). Philips Semiconductor.
2. Two-wire control is I
2
C-compatible.
3. All values referred to V
IHmin
= 0.9 V
DD
_IO and V
ILmax
= 0.1 V
DD
_IO levels. Sensor EXCLK = 27 MHz.
4. A device must internally provide a hold time of at least 300 ns for the S
DATA
signal to bridge the undefined region of the falling edge of S
CLK
.
5. The maximum t
HD;DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the S
CLK
signal.
6. A Fast-mode I
2
C-bus device can be used in a Standard-mode I
2
C-bus system, but the requirement t
SU;DAT
250 ns must then be met. This
will automatically be the case if the device does not stretch the LOW period of the S
CLK
signal. If such a device does stretch the LOW period
of the S
CLK
signal, it must output the next data bit to the S
DATA
line t
r
max + t
SU;DAT
= 1000 + 250 = 1250 ns (according to the Standard-mode
I
2
C-bus specification) before the S
CLK
line is released.
7. Cb = total capacitance of one bus line in pF.
I/O Timing
By default, the MT9M021/MT9M031 launches pixel
data, FV and LV with the falling edge of PIXCLK. The
expectation is that the user captures D
OUT
[11:0], FV and LV
using the rising edge of PIXCLK. The launch edge of
PIXCLK can be configured in register R0x3028. See
Figure 7 and Table 6 for I/O timing (AC) characteristics.
Figure 7. I/O Timing Diagram
EXTCLK
PIXCLK
Data[11:0]
LINE_VALID/
FRAME_VALID
Pxl_0 Pxl_1 Pxl_2 Pxl_n
t
PF
L
t
PL
L
t
FP
t
RP
t
F
t
R
90% 90% 90% 90%
10% 10% 10% 10%
t
EXTCLK
t
PD
t
PLH
t
PFH
FRAME_VALID Leads LINE_VALID
by 6 PIXCLKs
FRAME_VALID Trails LINE_VALID
by 6 PIXCLKs
MT9M021, MT9M031
www.onsemi.com
12
Table 6. I/O TIMING CHARACTERISTICS, PARALLEL OUTPUT (1.8 V V
DD
_IO) (Note 1)
Symbol
Definition Condition Min Typ Max Unit
f
EXTCLK
Input Clock Frequency 6 − 50 MHz
t
EXTCLK
Input Clock Period 20 − 166 ns
t
R
Input Clock Rise Time PLL Enabled − 3 4 ns
t
F
Input Clock Fall Time PLL Enabled − 3 4 ns
t
RP
PIXCLK Rise Time Slew Setting = 4 (Default) 2.3 − 4.6 ns
t
FP
PIXCLK Fall Time Slew Setting = 4 (Default) 3 − 4.4 ns
PIXCLK Duty Cycle 40 50 60 %
f
PIXCLK
PIXCLK Frequency (Note 2) Nominal Voltages, PLL Enabled 6 − 74.25 MHz
t
PD
PIXCLK to Data Valid Nominal Voltages, PLL Enabled −3 2.3 4.5 ns
t
PFH
PIXCLK to FV HIGH Nominal Voltages, PLL Enabled −3 1.5 4.5 ns
t
PLH
PIXCLK to LV HIGH Nominal Voltages, PLL Enabled −3 2.3 4.5 ns
t
PFL
PIXCLK to FV LOW Nominal Voltages, PLL Enabled −3 1.5 4.5 ns
t
PLL
PIXCLK to LV LOW Nominal Voltages, PLL Enabled −3 2 4.5 ns
1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C ambient at 90% of V
DD
_IO, and −30°C
at 110% of V
DD
_IO. All values are taken at the 50% transition point. The loading used is 20 pF.
2. Jitter from PIXCLK is already taken into account in the data for all of the output parameters.
Table 7. I/O TIMING CHARACTERISTICS, PARALLEL OUTPUT (2.8 V V
DD
_IO) (Note 1)
Symbol Definition Condition Min Typ Max Unit
f
EXTCLK
Input Clock Frequency 6 − 50 MHz
t
EXTCLK
Input Clock Period 20 − 166 ns
t
R
Input Clock Rise Time PLL Enabled − 3 4 ns
t
F
Input Clock Fall Time PLL Enabled − 3 4 ns
t
RP
PIXCLK Rise Time Slew Setting = 4 (Default) 2.3 − 4.6 ns
t
FP
PIXCLK Fall Time Slew Setting = 4 (Default) 3 − 4.4 ns
PIXCLK Duty Cycle 40 50 60 %
f
PIXCLK
PIXCLK Frequency (Note 2) Nominal Voltages, PLL Enabled 6 − 74.25 MHz
t
PD
PIXCLK to Data Valid Nominal Voltages, PLL Enabled −3 2.3 4 ns
t
PFH
PIXCLK to FV HIGH Nominal Voltages, PLL Enabled −3 1.5 4 ns
t
PLH
PIXCLK to LV HIGH Nominal Voltages, PLL Enabled −3 2.3 4 ns
t
PFL
PIXCLK to FV LOW Nominal Voltages, PLL Enabled −3 1.5 4 ns
t
PLL
PIXCLK to LV LOW Nominal Voltages, PLL Enabled −3 2 4 ns
1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C ambient at 90% of V
DD
_IO, and −30°C
at 110% of V
DD
_IO. All values are taken at the 50% transition point. The loading used is 20 pF.
2. Jitter from PIXCLK is already taken into account in the data for all of the output parameters.
Table 8. I/O RISE SLEW RATE (2.8 V V
DD
_IO) (Note 1)
Parallel Slew (R0x306E[15:13])
Condition Min Typ Max Unit
7 Default 1.08 1.77 2.72 V/ns
6 Default 0.77 1.26 1.94 V/ns
5 Default 0.58 0.95 1.46 V/ns
4 Default 0.44 0.70 1.08 V/ns
3 Default 0.32 0.51 0.78 V/ns
2 Default 0.23 0.37 0.56 V/ns
1 Default 0.16 0.25 0.38 V/ns
0 Default 0.10 0.15 0.22 V/ns
1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C ambient at 90% of V
DD
_IO, and −30°C
at 110% of V
DD
_IO. All values are taken at the 50% transition point. The loading used is 20 pF.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

MT9M021IA3XTMZH-GEVB

Mfr. #:
Buy MT9M021IA3XTMZH-GEVB
Manufacturer:
ON Semiconductor
Description:
Optical Sensor Development Tools 1.2 MP 1/3 GS CIS HB
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet