MT9M021, MT9M031
www.onsemi.com
4
TYPICAL CONFIGURATION AND PINOUT
Figure 2. Serial 4-lane HiSPi Interface
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two-wire speed.
3. This pull-up resistor is not required if the controller drives a valid logic level on S
CLK
at all times.
4. The parallel interface output pads can be left unconnected if the serial output interface is used.
5. ON Semiconductor recommends that 0.1 mF and 10 mF decoupling capacitors for each power supply are mounted as close as possible
to the pad. Actual values and results may vary depending on the layout and design considerations. Refer to the MT9M021/MT9M031 demo
headboard schematics for circuit recommendations.
6. ON Semiconductor recommends that analog power planes be placed in a manner such that coupling with the digital power planes is
minimized.
7. Although 4 serial lanes are shown, the MT9M021/MT9M031 supports only 2- or 3-lane HiSPi.
Notes:
FLASH
SLVS0_P
SLVS0_N
SLVS1_P
SLVS1_N
SLVS2_P
SLVS2_N
V
DD
_PLLV
DD
_IO V
AA
V
AA
_PIX
A
GND
D
GND
V
AA
_PIXV
AA
V
DD
_IO V
DD
S
DATA
S
CLK
EXTCLK
1.5 kW
2
1.5 kW
2,
3
OE_BAR
RESET_BAR
TEST
To Controller
From
Controller
Master Clock
(6−50 MHz)
I/O
Power
1
Core
Power
1
Analog
Power
1
Analog
Power
1
Analog
Ground
Digital
Ground
STANDBY
V
DD
_SLVS
HiSPi
Power
1
V
DD
_PLL
PLL
Power
1
SLVS3_P
SLVS3_N
SLVSC_P
SLVSC_N
V
DD
V
DD
_SLVS
7
7
