_______________Detailed Description
The MAX1661/MAX1662/MAX1663 convert 2-wire
SMBus serial data into three latched parallel outputs
(I/O1, I/O2, I/O3). These devices are intended to drive N-
channel and P-channel, high-side MOSFET switches in
load power-management systems. Readback capabili-
ties allow them to function as parallel-to-serial devices.
The MAX1661/MAX1662/MAX1663 operate from a single
supply with a typical quiescent current of 3µA, making
them ideal for portable applications (Figure 1).
SMBus Interface Operation
The SMBus serial interface is a 2-wire interface with
multi-mastering capability. From a software perspec-
tive, the MAX1661/MAX1662/MAX1663 appears as a
set of byte-wide registers that contain information con-
trolling the I/O_ pins, masking capabilities, and a con-
trol bit that determines which register is being
addressed. The 2-wire slave interface employs stan-
dard SMBus send-byte and receive-byte protocols.
SMBDATA and SMBCLK are Schmitt-triggered inputs
that can accommodate slower edges; however, the ris-
ing and falling edges should still be faster than 1µs and
300ns, respectively. Except for the stop and start con-
ditions, the SMBDATA input never transitions while
SMBCLK is high. A third interface line (SMBSUS) is
used to execute commands asynchronously from previ-
ously stored registers (see the section
SMBSUS
(Suspend-Mode) Input)
. This reduces the inherent
delay in a standard 2-wire serial interface. In the
receive-byte operation, the SMBus interface reads
back I/O states and thermal-shutdown status.
SMBus Addressing
Each slave device only responds to two addresses: its
own unique address and the alert response address. The
device’s unique address is determined at power-up
(Table 1). The three-level state of the address-select pin
(ADD) is only sampled upon power-on reset (POR) caus-
ing momentary input bias current of 100µA. The address
will not change until the part is power cycled. Stray
capacitance in excess of 50pF on the ADD pin when
floating may cause address recognition problems.
The normal start condition consists of a high-to-low
transition on SMBDATA while SMBCLK is high. After the
start condition, the master transmits a 7-bit address fol-
lowed by a single bit to determine whether the device is
sending or receiving (high = READ, low = WRITE). If
the address is correct, the MAX1661/MAX1662/
MAX1663 sends an acknowledgment pulse by pulling
SMBDATA low. Otherwise, the address is not recog-
nized and the device stays off the bus and waits until
another start condition occurs.
SMBus Send-Byte Commands
If the MAX1661/MAX1662/MAX1663 receives its correct
slave address (Table 1) followed by R/W low, it expects
to receive a byte of information. If the device detects a
start or stop condition prior to clocking in the byte of
data, it considers this an error condition and disregards
all of the data.
The MAX1661/MAX1662/MAX1663 generates a first
acknowledge after the write bit and another acknowledge
after the data. It executes the data byte at the rising edge
of SMBCLK following the second acknowledge, just prior
to the stop condition (Figure 2a). See Table 2 for send-
byte operations.
SMBSUS (Suspend-Mode) Input
The SMBus can write to either of the normal-data and
suspend-mode registers via the MSB (bit 7) of the
send-byte word (Table 2). The state of the SMBSUS
input selects which register contents (normal data or
suspend mode) are applied to the I/O_ pins. Driving
SMBSUS low selects the suspend-mode register, while
driving SMBSUS high selects the normal-data register.
This feature allows the system to select between two
different power-plane configurations asynchronously,
eliminating latencies introduced by the serial bus.
SMBSUS typically connects to the SUSTAT# signal in a
notebook computer.
SMBus Receive-Byte Operation
If the MAX1661/MAX1662/MAX1663 receives its correct
slave address, followed by R/W high, the device
becomes a slave transmitter (Figure 2b). After receiving
the address data, the device generates an acknowl-
edge during the acknowledge clock pulse and drives
SMBDATA in sync with SMBCLK. The SMB protocol
requires that the master terminate the read transmis-
sion by not acknowledging during the acknowledge bit
of SMBCLK. See Table 3 for receive-byte data format.
Figure 4 shows the complete receive-byte operation
timing diagram.
The logic states of the three I/O pins can be read over
the serial interface (Table 3). The state of the I/O pins is
sampled at the falling edge of the SMBCLK pulse that
follows the R/W bit and acknowledge bit (Figure 4). The
states of the I/O bits in the status register reflect the
Table 1. SMBus Addresses
MAX1661/MAX1662/MAX1663
Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Controllers with SMBus Interface
6 _______________________________________________________________________________________
ADD MAX1661 MAX1662 MAX1663
GND 0100000 0100001 0100010
High-Z
(floating)
0111100 0111101 0111110
V
CC
1001000 1001001 1001010
