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MAX1662EUB+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
Table 2. Format for Send-Byte Data
Send-Byte Format
MAX1661/MAX1662/MAX1663
Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Controllers with SMBus Interface
_______________________________________________________________________________________ 7
ADDRESS WRITE ACK DATA ACK
START
CONDITION
7 bits
1 bit
(low)
1 bit
(low)
8 bits
1 bit
(low)
STOP
CONDITION
Shaded = Slave Transmission
SMBCLK
I/O
A B C D
E
F G H
I
J
K
SMBDATA
t
SU:STA
t
HD:STA
t
LOW
t
HIGH
t
SU:DAT
t
HD:DAT
t
SU:STO
t
BUF
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
L
M
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE (OP/SUS BIT)
H = LSB OF DATA CLOCKED INTO SLAVE
I = SLAVE PULLS SMBDATA LINE LOW
J = ACKNOWLEDGE CLOCKED INTO MASTER
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION, DATA EXECUTED BY SLAVE
M = NEW START CONDITION
t
P
:
I/O
Figure 2a. SMBus Send-Byte Timing Diagram and Format
BIT NAME
POR STATE*
(MAX1661)
POR STATE*
(MAX1662/MAX1663)
FUNCTION
7 (MSB) SELECT N/A N/A
Writes data to normal register when high; writes data to suspend
register when low.
6 Mask SS 1 1 Masks START-STOP software interrupts when high.
5 Mask 3 1 1 Masks I/O3 interrupts when high.
4 Mask 2 1 1 Masks I/O2 interrupts when high.
3 Mask 1 1 1 Masks I/O1 interrupts when high.
2 I/O3 0 1 I/O output enable bit. I/O3 is on when this bit is low (low state).
1 I/O2 0 1 I/O output enable bit. I/O2 is on when this bit is low (low state).
0 I/O1 0 1 I/O output enable bit. I/O1 is on when this bit is low (low state).
*
Note: POR states apply to both suspend- and normal-mode registers.
current I/O pin states (i.e., they are not latched). There
is a 15µs data-setup time requirement, due to the slow
level translators needed for high-voltage (28V) opera-
tion. Data-hold time is zero.
Interrupts
The MAX1661/MAX1662/MAX1663 generate interrupts
(hardware and software) whenever the logic states of
the I/O pins change or when thermal shutdown occurs.
Interrupts are signaled with the hardware ALERT pin
MAX1661/MAX1662/MAX1663
Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Controllers with SMBus Interface
8 _______________________________________________________________________________________
and with the software START-STOP method (software
interrupts are discussed in the
START-STOP Software
Interrupt
section). The I/O interrupts can be masked
individually. In addition, the software START-STOP
interrupt can be masked independently. The power-on-
reset state masks the START-STOP interrupt, as well as
the individual I/O interrupts to the ALERT pin (Table 1).
The thermal-shutdown interrupt cannot be masked.
Note that excessive noise on the supply can cause
false interrupts (see
Applications Information
).
The MAX1661/MAX1662/MAX1663 are slave-only
devices that never initiate communications, except
when asserting an interrupt by forcing ALERT low, or
via the software START-STOP interrupt.
Alert Response Address (0001100)
The Alert Response (interrupt pointer) address pro-
vides quick fault identification for simple slave devices
that lack the complex, expensive logic needed to be a
bus master. When a slave device generates an inter-
Receive-Byte Format
ADDRESS READ ACK DATA
ACK
START
CONDITION
7 bits
1 bit
(high)
1 bit
(low)
8 bits
1 bit
(high-Z)
STOP
CONDITION
ACK = SMBDATA High
Shaded = Slave Transmission
SMBCLK
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
A B C D
E
F G H
I
J
SMBDATA
t
SU:STA
t
HD:STA
t
LOW
t
HIGH
t
SU:DAT
t
SU:STO
t
BUF
K
E = SLAVE PULLS SMBDATA LINE LOW
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO MASTER
H = LSB OF DATA CLOCKED INTO MASTER
I = ACKNOWLEDGE CLOCK PULSE
J = STOP CONDITION
K = NEW START CONDITION
Figure 2b. SMBus Receive-Byte Timing Diagram and Format
Table 3. Format for Receive-Byte Data
BIT NAME POR STATE FUNCTION LATCHED
7 (MSB) — 0 Not used —
6 — 0 Not used —
5 — 0 Not used —
4 — 0 Not used —
3 THSD N/A This bit indicates a thermal shutdown. Yes
2 Data 3 N/A This bit indicates the state of I/O3 (high or low). No
1 Data 2 N/A This bit indicates the state of I/O2 (high or low). No
0 Data 1 N/A This bit indicates the state of I/O1 (high or low). No
rupt, the host (Bus Master) interrogates the bus slave
devices via a special receive-byte operation that
includes the alert response address. The data returned
by this receive-byte operation is the address of the
offending slave device. The interrupt pointer address
can activate several different slave devices simultane-
ously. If more than one slave attempts to respond, bus
arbitration rules apply, with the lowest address code
going first. The other device(s) will not generate an
acknowledge and will continue to hold the ALERT line
low or repeat the START-STOP interrupt until serviced.
Clearing Interrupts via Alert Response
When a fault occurs, ALERT asserts and latches low. If
the fault is momentary and disappears before the
device is serviced, ALERT remains asserted. Normally,
the master sends out the Alert Response address fol-
lowed by a read bit (00011001). ALERT clears when
the device responds by successfully putting its
address on the bus. Reading the Alert Response
address is the
only
method for clearing hardware
and software interrupt latches. Clearing the interrupt
has no effect on the state of the status registers.
MAX1661/MAX1662/MAX1663
Serial-to-Parallel/Parallel-to-Serial Converters and
Load-Switch Controllers with SMBus Interface
_______________________________________________________________________________________ 9
t
DV
t
DV
SMBCLK
R/W BIT
CLOCKED
INTO SLAVE
ACKNOWLEDGE BIT
CLOCKED
INTO MASTER
MOST SIGNIFICANT
BIT OF DATA
CLOCKED INTO MASTER
SLAVE PULLING
SMBDATA LOW
SMBDATA
• • •
• • •
Figure 3. SMB Serial-Interface Timing—Acknowledge and Data Valid
START
ADDRESS
MSB
ADDRESS
LSB
SLAVE PULLS
SMBDATA LOW
4 ZEROS (NOT USED)
THSD DATA3 DATA2 DATA1
SLAVE
ACKNOWLEDGE
I/O
LATCHED
DATA
MSB
DATA LSB
SMBCLK
SMBDATA
R/W BIT
t
SU:I/O
(NOTE 1)
NOTE 1: THE SETUP AND HOLD TIMING LIMITS ARE ABSOLUTE LIMITS
(15µs MIN AND 0µs MIN, RESPECTIVELY) AND DO NOT NECESSARILY
CORRESPOND TO A PARTICULAR CLOCK EDGE.
(NOTE 1)
t
HD:I/O
SLAVE
ACKNOWLEDGE
(ACK)
Figure 4. I/O Read Timing Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

MAX1662EUB+T

Mfr. #:
Buy MAX1662EUB+T
Manufacturer:
Maxim Integrated
Description:
IC CONV SMBUS INTERFACE UMAX
Lifecycle:
New from this manufacturer.
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