Data Sheet ADP1972
Rev. B | Page 15 of 18
Selecting R
FREQ
for a Slave Device
To configure the ADP1972 as a slave device, drive V
SCFG
< 4.53 V.
When functioning as a slave device, the ADP1972 operates at
the frequency of the external clock applied to the SYNC pin. To
ensure proper synchronization, select R
FREQ
to set the frequency
to a value slightly slower than that of the master clock by using
the following equation:
R
FREQ
(SLAVE)
= 1.11 × R
FREQ
(MASTER)
(5)
where:
R
FREQ (MASTER)
is the resistor value that corresponds to the
frequency of the master clock applied to the SYNC pin.
R
FREQ (SLAVE)
is the resistor value that appropriately scales the
frequency for the slave device, and 1.11 is the R
FREQ
slave to
master ratio for synchronization.
The frequency of the slave device is set to a frequency slightly
lower than that of the master device to allow the digital
synchronization loop of the ADP1972 to synchronize to the
master clock period. The slave device has approximately a 30%
range capability to adjust to match the master clock value.
Setting R
FREQ (SLAVE)
to 1.11× larger than R
FREQ (MASTER)
runs the
synchronization loop in approximately the center of the
adjustment range.
Programming the External Clock Phase Shift
If a phase shift is not required for slave devices, connect SCFG
of each slave device to ground. For devices that require a phase
shifted version of the synchronization clock that is applied to
the SYNC pin of the slave devices, connect a resistor (R
SCFG
)
from SCFG to ground to program the desired phase shift. To
determine the R
SCFG
for a desired phase shift (φ
SHIFT
),
start by
calculating the frequency of the slave clock (f
SLAVE
).
)FREQ(SLAVE
SLAVE
R
f
4
10
(kHz) (6)
Next, calculate the period of the slave clock.
3
10
(kHz)
1
s
SLAVE
SLAVE
f
T
(7)
where:
T
SLAVE
is the period of the master clock in µs.
f
SLAVE
is the frequency of the master clock in kHz.
Next, determine the phase time delay (T
DELAY
) for the desired
phase shift (φ
SHIFT
) using the following equation:
360
sφ
s
SLAVE
SHIFT
DELAY
T
T
(8)
where:
T
DELAY
is the phase delay in µs.
φ
SHIFT
is the desired phase shift.
Lastly, to calculate the phase delay (T
DELAY
), use the following
equation:
R
SCFG
(kΩ) = 0.45 × R
FREQ (SLAVE)
(kΩ) + 50 × T
DELAY
(µs)
(9)
where:
R
SCFG
is the corresponding resistor for the desired phase shift
in kHz.
When using the phase shift feature, connect a capacitor of 47 pF
or greater in parallel with R
SCFG
.
Alternatively, the SCFG pin can be controlled with a voltage
source. When using an independent voltage source, ensure
V
SCFG
≤ VREG under all conditions. When the ADP1972 is
disabled via the EN pin or UVLO, VREG = 0 V, and the voltage
source must adjust accordingly to ensure V
SCFG
≤ VREG.
Figure 23 shows the internal voltage ramp of the ADP1972. The
voltage ramp has a well controlled 4 V p-p.
4.5V
T
0.5V
0.01T
0.99T
11884-027
Figure 23. Internal Voltage Ramp
PROGRAMMING THE MAXIMUM DUTY CYCLE
The ADP1972 is designed with a 98% (typical) internal
maximum duty cycle. By connecting a resistor from DMAX to
ground, the maximum duty cycle can be programmed at any
value from 0% to 98%, using the following equation:
5.10
5.21
%
FREQ
DMAXFREQ
MAX
R
RV
D (10)
where:
D
MAX
is the programmed maximum duty cycle.
V
FREQ
is 1.252 V (typical).
R
DMAX
is the value of the resistance used to program the
maximum duty cycle.
R
FREQ
is the frequency set resistor used in the application.
The current source of DMAX is equivalent to the programmed
current of the FREQ pin:
FREQ
FREQ
FREQDMAX
R
V
II (11)
where I
DMAX
= I
FREQ
= the current programmed on the
FREQ pin.
The maximum allowable duty cycle of the ADP1972 is 98%
(typical). If the resistor on DMAX sets a maximum duty cycle
larger than 98%, the ADP1972 defaults to its internal
maximum. If the 98% internal maximum duty cycle is sufficient
for the application, tie the DMAX pin to VREG or leave it floating.
The C
DMAX
capacitor connected from the DMAX pin to GND
must be 47 pF or greater.
