Data Sheet ADP1972
Rev. B | Page 11 of 18
EN/SHUTDOWN
The EN input turns the ADP1972 on or off. The EN pin of the
ADP1972 can operate from voltages up to 60 V and is designed
with stable ±20% thresholds for precision enable control. When
the EN voltage is less than 1.22 V (typical), the ADP1972 shuts
down, driving both DL and DH low. When the ADP1972 is shut
down, the VIN supply current is 15 μA (typical). When the EN
voltage is greater than 1.25 V (typical), the ADP1972 is enabled.
The device can be disabled via the EN pin, a fault condition
indicated by a TSD event, a UVLO condition, or an external
fault condition signaled via the FAULT pin.
UNDERVOLTAGE LOCKOUT (UVLO)
There is internal UVLO for the VIN pin. When VIN rises, the
UVLO does not allow the ADP1972 to turn on unless VIN is
greater than 5.71 V (typical). When VIN falls, the UVLO disables
the device when VIN drops below 5.34 V (typical). The UVLO
prevents potentially erratic operation of the application at low
input voltages that may damage the ADP1972 and the external
circuitry. The UVLO levels have ~370 mV of hysteresis to ensure
glitch free startup.
SOFT START
The ADP1972 is equipped with a programmable soft start that
prevents output voltage overshoot during startup. When the
ADP1972 is enabled with the EN pin, the VREG voltage begins
rising to 5 V. When VREG reaches 90% of its 5 V (typical) value,
the 5 μA (typical) internal soft start current (I
SS
) begins charging
the soft start capacitor (C
SS
), causing the voltage on the SS pin
(V
SS
) to rise. While V
SS
is less than 0.52 V (typical), the ADP1972
switching control remains disabled.
When V
SS
reaches 0.52 V (typical), switching is enabled, and
regulation of the ADP1972 control loop begins. As C
SS
continues
to charge and V
SS
rises, the PWM duty cycle gradually increases,
allowing the output voltage to rise linearly with little to no over-
shoot during startup. C
SS
charges and V
SS
rises until V
SS
reaches
the internal VREG voltage (5 V typical). When the internal system
duty cycle is less than the soft start duty cycle, the internal control
loop takes control of the ADP1972. See Figure 18 for a soft start
diagram.
There is an active, internal, pull-down resistor on the SS pin
that discharges C
SS
when the device shuts down to prevent a
fault from occurring.
VREG
VOUT
0.52V
0V
V
SS
ENABLE
ADP1972
BEGIN
REGULATION
t
REG
11884-022
Figure 18. Soft Start Diagram
OPERATING MODES
The ADP1972 can be programmed to operate as an asynchronous
boost or as an asynchronous buck. If the MODE pin is driven
low by less than 1.05 V (typical), then the ADP1972 operates in
a boost configuration. A boost configuration is ideal for power
recycling and discharging in battery charging applications.
When the MODE pin is driven high by greater than 1.20 V
(typical), the ADP1972 operates in a buck configuration for
battery charging. See Figure 19 and Figure 20 for the ADP1972
behavior in each mode. When the ADP1972 is enabled, the
internal LDO regulator connected to the VREG pin also powers up.
On the rising edge of VREG, the state of the MODE pin is latched,
preventing the mode of operation from being changed while the
device is enabled. To change between boost and buck modes of
operation, shutdown or disable the ADP1972, adjust the MODE
pin to change the operating mode, and restart the system.
The operating mode can be changed when the EN pin is driven
low, the FAULT pin is driven low, or the ADP1972 is disabled
via a TSD event or UVLO condition. On the rising edge of the
FAULT control signal, the state of the MODE pin is latched,
preventing the mode of operation from being changed while the
device is enabled.
0.5V
4.5V
BOOST MODE CONFIGURATION
MODE ≤ 1.05V (TYPICAL)
V
SCFG
≥ 4.53V (TYPICAL)
COMP
0V
DH
DL
0V
INTERNAL RAMP
(4V p-p)
VREG (5V TYPICAL)
VREG (5V TYPICAL)
0V
11884-023
Figure 19. Signal Diagram for Boost Configuration
0.5V
4.5V
BUCK MODE CONFIGURATION
MODE ≥ 1.2V (TYPICAL)
V
SCFG
≥ 4.53V (TYPICAL)
COMP
0V
DH
DL
0V
INTERNAL RAMP
(4V p-p)
VREG (5V TYPICAL)
VREG (5V TYPICAL)
0V
11884-024
Figure 20. Signal Diagram for Buck Configuration
