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ADP1972ARUZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
ADP1972 Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ADP1972
TOP VIEW
(Not to Scale)
DH
VREG
VIN
SYNC
MODE
EN
DL
FAULT
GND
SENSE
GND
SCFG
SS
COMP
DMAX
FREQ
CL
1
1884-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 DL Logic Drive Low Output for External Low-Side MOSFET Driver.
2 DH Logic Drive High Output for External High-Side MOSFET Driver.
3 VREG
Internal Low Dropout (LDO) Voltage Regulator Output and Internal Bias Supply. A bypass capacitance of 1 µF or
greater from this pin to ground is required.
4 VIN High Input Voltage Supply Pin. Bypass this pin with a 4.7 µF capacitor to ground.
5 EN Logic Enable Input. Drive EN logic low to shut down the device. Drive EN logic high to turn on the device.
6
MODE
Mode Select. Drive MODE logic low to place the device in boost/recycle mode. Drive MODE logic high to place
the device in buck/charge mode of operation.
7 SYNC
Synchronization Pin. This pin is used as an input and synchronized to an external clock or used as an output
clock to synchronize with other channels.
8 FAULT
Fault Input Pin. Signaled by an overcurrent protection (OCP) or overvoltage protection (OVP) fault condition on
the companion ASIC, AD8450. The ADP1972 is disabled until this pin is logic high.
9 COMP
Output Error Amplifier Signal from the companion ASIC, AD8450. This pin is the error input to the ADP1972 and
is compared internally to the linear ramp to produce the PWM signal. Do not leave this pin floating.
10 SS
Soft Start Control Pin. A capacitor connected from SS to ground brings the output up slowly during power-up
and reduces the inrush current.
11 DMAX
Maximum Duty Cycle Input. Connect an external resistor to ground to set the maximum duty cycle. If the 98%
internal maximum duty cycle is sufficient for the application, tie this pin to VREG. If DMAX is left floating, this
pin is internally tied to VREG.
12 FREQ
Frequency Set Pin. Connect an external resistor between this pin and ground to set the frequency between
50 kHz and 300 kHz.
13 SCFG
Synchronization Configuration Input. Drive V
SCFG
≥ 4.53 V to configure SYNC as an output clock signal. Drive
V
SCFG
< 4.25 V to configure SYNC as an input. Connect a resistor to ground with 0.65 V < V
SCFG
< 4.25 V to
introduce a phase shift to the synchronized clock. Drive V
SCFG
≤ 0.5 V to configure SYNC as an input with no
phase shift so that it synchronizes the device to an external clock source. If SCFG is left floating, the SYNC pin
is internally tied to VREG, and SYNC is configured as an output.
14 GND Power and Analog Ground Pin.
15 GND
SENSE
Ground Sense for the Current-Limit Setting Resistor.
16 CL
Current-Limit Programming Pin. Connect a current-limit sense resistor in series with the FET source to set the
peak current limit.
Rev. B | Page 6 of 18
Data Sheet ADP1972
TYPICAL PERFORMANCE CHARACTERISTICS
V
VIN
= V
EN
= V
FAULT
= 24 V, V
MODE
= V
CL
= V
SS
= V
COMP
= 0 V, T
A
= 25°C, unless otherwise noted.
5.8
5.7
5.6
5.5
5.4
5.3
5.2
–40 –5
30
65 100
VIN UVLO THRESHOLD (V)
TEMPERATURE (°C)
RISING
FALLING
1
1884-003
Figure 3. Input Voltage UVLO Threshold vs. Temperature,
V
FAULT
= 0 V
Figure 4. Shutdown Current vs. Input Voltage, V
EN
= 0 V and V
FAULT
= 0 V
Figure 5. Nonswitching Quiescent Current vs. Input Voltage (SYNC = Floating)
Figure 6. EN Pin Current vs. EN Pin Voltage, V
EN
= 5 V and V
FAULT
= 0 V
1.25
1.20
1.21
1.22
1.23
1.24
–40 –5 30 65 100
EN PIN THRESHOLD (V)
TEMPERATURE (°C)
RISING
FALLING
11884-008
Figure 7. EN Pin Threshold vs. Temperature, V
FAULT
= 0 V
5.00
4.88
4.90
4.92
4.94
4.96
4.98
–40 12080400
SS PIN CURRENT (µA)
TEMPERATURE (°C)
V
IN
= 6V
V
IN
= 24V
V
IN
= 60V
11884-009
Figure 8. SS Pin Current vs. Temperature
Rev. B | Page 7 of 18
ADP1972 Data Sheet
Figure 9. Maximum Internal Duty Cycle vs. Input Voltage,
R
FREQ
= 100 kΩ, V
COMP
= 5 V, and No Load on DL, DH, or DMAX
450
0
50
100
150
200
250
300
400
350
0 20 40 60 80 100
R
DMAX
(kΩ)
DUTY CYCLE (%)
T
A
= –40°C
T
A
= +25°C
T
A
= +125°C
11884-011
Figure 10. R
DMAX
vs. Duty Cycle, R
FREQ
= 100 kΩ, V
COMP
= 5 V, and
No Load on DL or DH
100
80
60
40
20
0
0.5 5.04.54.0
3.53.02.5
2.01.51.0
DUTY CYCLE (%)
V
COMP
(V)
T
A
= –40°C
T
A
= +25°C
T
A
= +125°C
11884-018
Figure 11. Duty Cycle vs. V
COMP
, R
FREQ
= 100 kΩ, and
No Load on DL, DH, or DMAX
210
30
50
70
90
110
130
150
170
190
50 100 150
200
250
300
R
FREQ (MASTER)
(kΩ)
f
SET
(kHz)
1
1884-015
Figure 12. R
FREQ (MASTER)
vs. Switching Frequency (f
SET
)
Figure 13. VREG vs. Input Voltage, No Load
5.020
4.980
4.985
4.990
4.995
5.000
5.005
5.010
5.015
0 54321
VREG (V)
LOAD CURRENT (mA)
T
A
= –40°C
T
A
= +25°C
T
A
= +85°C
T
A
= +125°C
11884-017
Figure 14. VREG vs. Load Current
Rev. B | Page 8 of 18
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

ADP1972ARUZ-RL

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Switching Controllers GSM Power Management System
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