8
LTC1380/LTC1393
APPLICATIONS INFORMATION
WUU
U
TI I G DIAGRA
UW W
SDA FROM
HOST
SDA FROM
LTC1380/LTC1393
SCL
D
O
X0A0A10011*
*0 FOR LTC1380, 1 FOR LTC1393
X X X EN C2 C1 C0
S
t
SU:STA
S P
t
HD:DAT
t
SU:DAT
t
HD:STA
t
r
t
f
t
LOW
t
HIGH
t
BUF
t
SU:STO
t
OFF
t
ON
t
OPEN
ADDRESS BYTE COMMAND BYTE
Theory of Operation
The LTC1380/LTC1393 are analog input multiplexers with
an SMBus digital interface. The LTC1380 is a single-ended
8-to-1 multiplexer; the LTC1393 is a differential 4-to-1
mulitplexer. The LTC1380 operates on either bipolar or
unipolar supplies, the LTC1393 operates on a single
supply. The minimum V
CC
supply for the LTC1380/LTC1393
is 2.7V. The maximum supply voltage (V
CC
to V
EE
for the
LTC1380, V
CC
for the LTC1393) should not exceed 14V.
The multiplexer switches operate within the entire power
supply range. The LTC1380 V
CC
and V
EE
supplies can be
offset such as 2.7V/–11V and 11V/–3V.
Serial Interface
The LTC1380/LTC1393 serial interface supports SMBus
send byte protocol as shown below with two interface
signals, SCL and SDA.
A send byte protocol is initiated by the SMBus host with a
start bit followed by a 7-bit address code and a write bit.
Each slave compares the address code with its address.
The send byte write bit is Low. The selected slaves then
reply with an acknowledge bit by pulling the SDA line Low.
Next, the host sends an 8-bit command byte. When the
selected slave receives the whole command byte, it ac-
knowledges and retains the command byte in the shift
register. The host can terminate the serial transfer with a
stop bit or communicate with another slave device with a
repeat start. When a repeat start occurs but the slave is not
selected, the command byte data is kept in the shift
register but the multiplexer control is not updated. The
multiplexer control latches the new command from the
shift register on the first stop bit after a successful com-
mand byte transfer. This allows the host to synchronize
several slave devices with a single stop bit. A1 and A0
select one of the four possible LTC1380/LTC1393 ad-
dresses as shown in Table 1. This allows up to four similar
devices to share the same SMBus, expanding the multi-
plexer to 32 single-ended channels with the LTC1380; 16
differential channels with the LTC1393. The first stop bit
after a successful send byte transfer will latch in the
multiplexer control bits (EN, C2, C1 and C0) and initiate a
break-before-make sequence.
S10010A1A0WAXXXXENC2C1C0AP
LTC1380 Send Byte Protocol
S1001
ADDRESS BYTE
S = SMBus START BIT
P = SMBus STOP BIT (THE FIRST STOP BIT AFTER A SUCCESSFUL COMMAND BYTE
UPDATES THE MULTIPLEXER CONTROL LATCH)
A = ACKNOWLEDGE BIT FROM LTC1380/LTC1393
W = WRITE COMMAND BIT
A1, A0 = ADDRESS BITS
EN, C2, C1, C0 = MULTIPLEXER CONTROL BITS
1A1A0WAXXXXENC2C1C0AP
LTC1393 Send Byte Protocol
COMMAND BYTE
