DS081 (v2.0) March 31, 2006 www.xilinx.com 1
Product Specification
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Features
• Low power 3.3V 512 macrocell CPLD
• 7.0 ns pin-to-pin logic delays
• System frequencies up to 135 MHz
• 512 macrocells with 12,000 usable gates
• Available in small footprint packages
- 208-pin PQFP (180 user I/O)
- 256-ball FBGA (212 user I/O)
- 324-ball FBGA (260 user I/O)
• Optimized for 3.3V systems
- Ultra low power operation
- Typical Standby Current of 18 μA at 25°
C
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- Fast Zero Power™ (FZP) CMOS design
technology
- 3.3V PCI electrical specification compatible outputs
(no internal clamp diode on any input or I/O)
• Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 clocks available per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
• Fast ISP programming times
• Port Enable pin for additional I/O
• 2.7V to 3.6V supply voltage at industrial grade voltage
range
• Programmable slew rate control per output
• Security bit prevents unauthorized access
• Refer to the CoolRunner™ XPLA3 family data sheet
(DS012
) for architecture description
Description
The CoolRunner™ XPLA3 XCR3512XL device is a 3.3V,
512 macrocell CPLD targeted at power sensitive designs
that require leading edge programmable logic solutions. A
total of 32 function blocks provide 12,000 usable gates.
Pin-to-pin propagation delays are as fast as 7.0 ns with a
maximum system frequency of 135 MHz.
TotalCMOS Design Technique for Fast
Zero Power
CoolRunner XPLA3 CPLDs offer a TotalCMOS™ solution,
both in process technology and design technique. This fam-
ily employs a cascade of CMOS gates to implement its sum
of products, instead of the traditional sense amp approach.
This CMOS gate implementation allows Xilinx to offer
CPLDs that are both high performance and low power,
breaking the paradigm that to have low power, you must
have low performance. Refer to Figure 1 and Table 1 show-
ing the I
CC
vs. Frequency of our XCR3512XL TotalCMOS
CPLD (data taken with 32 resetable up/down, 16-bit
counters at 3.3V, 25°C).
0
XCR3512XL: 512 Macrocell CPLD
DS081 (v2.0) March 31, 2006
014
Product Specification
R
Figure 1: Typical I
CC
vs. Frequency at V
CC
= 3.3V, 25°C
30
270
300
240
210
180
150
120
90
60
0 20 40 60 80 100 120
Frequency (MHz)
Typical ICC (mA)
Table 1: Typical I
CC
vs. Frequency at V
CC
= 3.3V, 25°C
Frequency (MHz) 0 1 10 20 40 60 80 100 120
Typical I
CC
(mA) 0.018 2.57 25.5 50.8 100.3 147.9 193.5 237.8 281.6
