DS1670
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POWER-UP/POWER-DOWN CONSIDERATIONS
The DS1670 was designed to operate with a power supply of 3.3V. When 3.3V are applied within
nominal limits, the device becomes fully accessible after t
RPU
(250ms typical). Before t
RPU
elapses, all
inputs are disabled. When V
CC
drops below 2.88V (typical), the RST pin is driven low. When V
CC
drops
below the lower of 2.7V (typical) or the battery voltage, the device is switched over to the backup power
supply.
During power-up, when V
CC
returns to an in-tolerance condition, the RST pin is kept in the active state
for 250ms (typical) to allow the power supply and microprocessor to stabilize.
ADDRESS/COMMAND BYTE
The command byte for the DS1670 is shown in Figure 2. Each data transfer is initiated by a command
byte. Bits 0 through 6 specify the addresses of the registers to be accessed. The MSB (bit 7) is the
Read/Write bit. This bit specifies whether the accessed byte will be read or written. A read operation is
selected if bit 7 is a 0 and a write operation is selected if bit 7 is a 1. The address map for the DS1670 is
shown in Figure 3.
ADDRESS/COMMAND BYTE Figure 2
7 6 5 4 3 2 1 0
RD
WR
A6 A5 A4 A3 A2 A1 A0
DS1670 ADDRESS MAP Figure 3
BIT 7 BIT 0
00 0 10 SECONDS SECONDS
01 0 10 MINUTES MINUTES
10 HR
02 0
12
24
A/P
10 HR HOURS
03 0 0 0 0 0 DAY
04 0 0 10 DATE DATE
05 0 0 0 10
MO.
MONTH
06 10 YEAR YEAR
07 M 10 SEC ALARM SECONDS ALARM
08 M 10 MIN ALARM MINUTES ALARM
10 HR
09 M
12
24
A/P
10 HR HOUR ALARM
0A M 0 0 0 DAY ALARM
0B CONTROL REGISTER
0C STATUS REGISTER
0D WATCHDOG REGISTER
0E ADC REGISTER
0F
7F
RESERVED
DS1670
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CLOCK, CALENDAR, AND ALARM
The time and calendar information is accessed by reading/writing the appropriate register bytes. Note that
some bits are set to 0. These bits will always read 0 regardless of how they are written. Also note that
registers 0 Fh to 7 Fh are reserved. These registers will always read 0 regardless of how they are written.
The contents of the time, calendar, and alarm registers are in the Binary-Coded Decimal (BCD) format.
The DS1670 can run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the
12-hour or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5
is the AM/PM bit with logic 1 being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23
hours).
The DS1670 also contains a time of day alarm. The alarm registers are located in registers 07h to 0 Ah.
Bit 7 of each of the alarm registers are mask bits (see Table 1). When all of the mask bits are logic 0, an
alarm will occur once per week when the values stored in timekeeping registers 00h to 03h match the
values stored in the time of day alarm registers. An alarm will be generated every day when mask bit of
the day alarm register is set to 1. An alarm will be generated every hour when the day and hour alarm
mask bits are set to 1. Similarly, an alarm will be generated every minute when the day, hour, and minute
alarm mask bits are set to 1. When day, hour, minute, and seconds alarm mask bits are set to 1, an alarm
will occur every second.
TIME OF DAY ALARM BITS Table 1
ALARM REGISTER MASK BITS (BIT 7)
SECONDS MINUTES HOURS DAYS
DESCRIPTION
1 1 1 1 Alarm once per second.
0 1 1 1 Alarm when seconds match.
0 0 1 1 Alarm when minutes and seconds match
0 0 0 1 Alarm when hours, minutes and seconds match.
0 0 0 0 Alarm when day, hours, minutes and seconds.
SPECIAL PURPOSE REGISTERS
The DS1670 has two additional registers (control register and status register) that control the real-time
clock and interrupts.
CONTROL REGISTER
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
EOSC
WP AIS1 AIS0 0 0 0 AIE
EOSC (Enable Oscillator). This bit when set to logic 0 will start the oscillator. When this bit is set to a
logic 1, the oscillator is stopped and the DS1670 is placed into a low-power standby mode with a current
drain of less than 200nA when in battery-backup mode. When the DS1670 is powered by V
CC
, the
oscillator is always on regardless of the status of the
EOSC bit; however, the real-time clock is
incremented only when
EOSC
is a logic 0.
WP (Write Protect). Before any write operation to the real time clock or any other registers, this bit
must be logic 0. When high, the write-protect bit prevents a write operation to any register.
DS1670
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AIS0-AIS1 (Analog Input Select). These 2 bits are used to determine the analog input for the analog-to-
digital conversion. Table 2 lists the specific analog input that is selected by these two bits.
AIE (Alarm Interrupt Enable). When set to a logic 1, this bit permits the Interrupt Request Flag (IRQF)
bit in the status register to assert INT. When the AIE bit is set to logic 0, the IRQF bit does not initiate the
INT signal.
ANALOG INPUT SELECTION Table 2
AIS1 AIS0 ANALOG INPUT
0 0 NONE
0 1 AIN0
1 0 AIN1
1 1 AIN2
STATUS REGISTER
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CU LOBAT 0 0 0 0 0 IRQF
CU (Conversion Update In Progress). When this bit is a 1, an update to the ADC Register (register
0Eh) will occur within 488ms. When this bit is a 0, an update to the ADC Register will not occur for at
least 244ms.
LOBAT (Low Battery Flag). This bit reflects the status of the backup power source connected to the
V BAT pin. When V
BAT
is greater than 2.5V, LOBAT is set to a logic 0. When V
BAT
is less than 2.3 volts,
LOBAT is set to a logic 1.
IRQF (Interrupt Request Flag). A logic 1 in the Interrupt Request Flag bit indicates that the current
time has matched the time of day Alarm registers. If the AIE bit is also a logic 1, the INT pin will go
high. IRQF is cleared by reading or writing to any of the alarm registers.
POWER-UP DEFAULT STATES
These bits are set to a one upon initial power-up:
EOSC
, TD1 and TD0. These bits are cleared upon
initial power-up: WP, AIS1, and AIS0.
NONVOLATILE SRAM CONTROLLER
The DS1670 provides automatic backup and write protection for external SRAM. This function is
provided by gating the chip enable signals and by providing a constant power supply through the V
CCO
pin. The DS1670 was specifically designed with the Intel 80186 and 386EX microprocessors in mind. As
such, the DS1670 can provide access to the external SRAM in either byte-wide or word-wide format.
This capability is provided by the chip enable scheme. Three input signals and two output signals are
used for enabling the external SRAM(s) (see Figure 4).
CEI
(chip enable in), BHE (byte high enable),
and
BLE (byte low enable) are used for enabling either one or two external SRAMs through the CEOL
(chip enable low) and the CEOH (chip enable high) outputs. Table 3 illustrates the function of these pins.

DS1670S+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Real Time Clock Portable System Controller
Lifecycle:
New from this manufacturer.
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