DS1670S+ Datasheet DS1670E+, DS1670S+ | P7-P9

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The DS1670 nonvolatilizes the external SRAM(s) by write protecting the SRAM(s) and by providing a

back-up power supply in the absence of V

. When V

falls below 2.88V (typical), access to the

external SRAM(s) are prohibited by forcing CEOL and CEOH high regardless of the level of CEI , BLE ,

and

BHE . Also at this point, the SRAM power supply (V

CCO

) is switched from V

to V

BAT

. Upon power-

up, access is prohibited until the end of t

RPU

EXTERNAL SRAM CHIP ENABLE Table 3

CEI

BHE

BLE

CEOL CEOH

FUNCTION

0 0 0 0 0 Word Transfer

0 0 1 1 0 Byte Transfer in upper half of data bus (D15-D8)

0 1 0 0 1 Byte Transfer in lower half of data bus (D7-D0)

0 1 1 1 1 External SRAMs disabled

1 X X 1 1 External SRAMs disabled

EXTERNAL SRAM INTERFACE (WORD-WIDE) TO THE DS1670 Figure 4

MICROPROCESSOR MONITOR

The DS1670 monitors three vital conditions for a microprocessor: power supply, software execution, and

external override.

First, a precision temperature-compensated reference and comparator circuit monitors the status of V

When an out-of-tolerance condition occurs, an internal power-fail signal is generated which forces the

RST

pin to the active state, thus warning a processor-based system of impending power failure. The

power-fail trip point is 2.88V (typical). When V

returns to an in-tolerance condition upon power-up,

the reset signal is kept in the active state for 250ms (typical) to allow the power supply and

microprocessor to stabilize. Note, however, that if the

EOSC bit is set to a logic 1 (to disable the oscillator

during battery-backup mode), the reset signal will be kept in an active state for 250ms plus the startup

time of the oscillator.

The second monitoring function is pushbutton reset control. The DS1670 provides for a pushbutton

switch to be connected to the RST output pin. When the DS1670 is not in a reset cycle, it continuously

monitors the

RST signal for a low-going edge. If an edge is detected, the DS1670 will debounce the

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switch by pulling the RST line low. After the internal 250ms timer has expired, the DS1670 will continue

to monitor the RST line. If the line is still low, the DS1670 will continue to monitor the line looking for a

rising edge. Upon detecting release, the DS1670 will force the RST line low and hold it low for 250ms.

The third microprocessor monitoring function provided by the DS1670 is a watchdog timer. The

watchdog timer function forces RST to the active state when the ST input is not stimulated within the

predetermined time period. The time period is set by the Time Delay (TD) bits in the Watchdog Register.

The time delay can be set to 250ms, 500ms, or 1000ms (see Figure 5). If TD0 and TD1 are both set to 0,

the watchdog timer is disabled. When enabled, the watchdog timer starts timing out from the set time

period as soon as RST is inactive. The default setting is for the watchdog timer to be enabled with

1000ms time delay. If a high-to-low transition occurs on the ST input pin prior to timeout, the watchdog

timer is reset and begins to time-out again. If the watchdog timer is allowed to timeout, then the RST

signal is driven to the active state for 250ms (typical). The ST input can be derived from microprocessor

address signals, data signals, and/or control signals. To guarantee that the watchdog timer does not

timeout, a high-to-low transition must occur at or less than the minimum period.

WATCHDOG TIMEOUT CONTROL Figure 5

WATCHDOG REGISTER

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0 0 0 0 0 0 TD1 TD0

WATCHDOG TIMEOUT

TD1 TD0 WATCHDOG TIMEOUT

0 0 Watchdog disabled

0 1 250ms

1 0 500ms

1 1 1000ms

ANALOG-TO-DIGITAL CONVERTER

The DS1670 provides a 3-channel, 8-bit analog-to-digital converter. The ADC reference voltage (2.55V

typical) is derived from an on-chip band-gap circuit. Three multiplexed analog inputs are provided

through the AIN0, AIN1, and AIN2 pins. The ADC is monotonic (no missing codes) and uses a

successive approximation technique to convert the analog signal into a digital code. An A/D conversion is

the process of assigning a digital code to an analog input voltage. This code represents the input value as

a fraction of the full-scale voltage (FSV) range. Thus, the FSV range is then divided by the ADC into 256

codes (8 bits). The FSV range is bounded by an upper limit equal to the reference voltage and the lower

limit, which is ground. The DS1670 has a FSV of 2.55V (typical) that provides a resolution of 10mV. An

input voltage equal to the reference voltage converts to FFh while an input voltage equal to ground

converts to 00h. The relative linearity of the ADC is ±0.5 LSB.

The ADC selects from one of three different analog inputs (AIN0–AIN2). The input that is selected is

determined by the Analog Input Select (AIS) bits in the Control Register. Table 2 lists the specific analog

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input that is selected by these 2 bits. Note also that the converter can be turned off by these bits to reduce

power. When the ADC is turned on by setting AIS0 and AIS1 to any value other than 0,0 the analog input

voltage is converted and written to the ADC Register within 488ms. An internal analog filter at the input

reduces high frequency noise. Subsequent updates occur approximately every 10ms. If AIS0 and/or AIS1

are changed, updates will occur at the next 10ms conversion time.

The Conversion Update In Progress (CU) bit in the Status Register indicates when the ADC Register can

be read. When this bit is a 1, an update to the ADC Register will occur within 488ms maximum.

However, when this bit is 0 an update will not occur for at least 244ms. The CU bit should be polled

before reading the ADC Register to ensure that the contents are stable during a read cycle. Once a read

cycle to the ADC Register has been started, the DS1670 will not update that register until the read cycle

has been completed. It should also be mentioned that taking CS low will abort the read cycle and will

allow the ADC Register to be updated.

Figure 6 illustrates the timing of the CU bit relative to an instruction to begin conversion and the

completion of that conversion.

CU BIT TIMING Figure 6

3-WIRE SERIAL INTERFACE

Communication with the DS1670 is accomplished through a simple 3-wire interface consisting of the

Chip Select (CS), Serial Clock (SCLK) and Input/Output (I/O) pins.

All data transfers are initiated by driving the CS input high. The CS input serves two functions. First, CS

turns on the control logic, which allows access to the shift register for the address/command sequence.

Second, the CS signal provides a method of terminating either single byte or multiple byte (burst) data

transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For data input, data must

be valid during the rising edge of the clock and data bits are output on the falling edge of the clock. If the

CS input goes low, all data transfer terminates and the I/O pin goes to a high-impedance state.

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DS1670S+

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Description:

Real Time Clock Portable System Controller

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DS1670S+

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