AD7732BRUZ Datasheet AD7732BRUZ, AD7732BRUZ-REEL, AD7732BRUZ-REEL7 | P22-P24

AD7732

Rev. A | Page 21 of 32

MD2 MD1 MD0 Operating Mode

0 0 0

Idle Mode

The default mode after power-on or reset.

The AD7732 automatically returns to this mode after any calibration or after a single conversion.

0 0 1

Continuous Conversion Mode

The AD7732 performs a conversion on the specified channel. After the conversion is complete, the relevant channel

data register and channel status register are updated, the relevant RDY bit in the ADC status register is set, and the

AD7732 continues converting on the next enabled channel. The part will cycle through all enabled channels until it is

put into another mode or reset. The cycle period will be the sum of all enabled channels’ conversion times, set by the

corresponding channel conversion time registers.

0 1 0

Single Conversion Mode

The AD7732 performs a conversion on the specified channel. After the conversion is complete, the relevant channel

data register and channel status register are updated, the relevant RDY bit in the ADC status register is set, the RDY

goes low, the MD2–MD0 bits are reset, and the AD7732 returns to idle mode. Requesting a single conversion ignores

the channel setup register enable bits; a conversion will be performed even if that channel is disabled.

0 1 1

Power-Down (Standby) Mode

The ADC and the analog front end (internal buffer) go into the power-down mode.

The AD7732 digital interface can still be accessed. The CLKDIS bit works separately, and the MCLKOUT mode is not

affected by the power-down (standby) mode.

1 0 0

ADC Zero-Scale Self-Calibration Mode

A zero-scale self-calibration is performed on internally shorted ADC inputs.

After the calibration is complete, the contents of the ADC zero-scale calibration register are updated, all RDY bits in the

ADC status register are set, the RDY pin goes low, the MD2–MD0 bits are reset, and the AD7732 returns to idle mode.

1 0 1 For Future Use.

1 1 0

Channel Zero-Scale System Calibration Mode

A zero-scale system calibration is performed on the selected channel. An external system zero-scale voltage should be

provided at the AD7732 analog input and should remain stable for the duration of the calibration. After the calibration

is complete, the contents of the corresponding channel zero-scale calibration register are updated, all RDY bits in the

ADC status register are set, the RDY

pin goes low, the MD2–MD0 bits are reset, and the AD7732 returns to idle mode.

1 1 1

Channel Full-Scale System Calibration Mode

A full-scale system calibration is performed on the selected channel. An external system full-scale voltage should be

provided at the AD7732 analog input and this voltage should remain stable for the duration of the calibration. After

the calibration is complete, the contents of the corresponding channel full-scale calibration register are updated, all

RDY bits in the ADC status register are set, the RDY

pin goes low, the MD2–MD0 bits are reset, and the AD7732 returns

to idle mode.

AD7732

Rev. A | Page 22 of 32

DIGITAL INTERFACE DESCRIPTION

The

RESET

pin can be used to reset the AD7732. When not

used, connect this pin to DV

Hardware

The AD7732 serial interface can be connected to the host

device via the serial interface in several different ways.

The AD7732 interface can be reduced to just two wires

connecting the DIN and DOUT pins to a single bidirectional

data line. The second signal in this 2-wire configuration is the

SCLK signal. The host system should change the data line

direction with reference to the AD7732 timing specification

(see the Bus Relinquish Time in Table 2). The AD7732 cannot

operate in the continuous read mode in 2-wire serial interface

configuration.

The

pin can be used to select the AD7732 as one of several

circuits connected to the host serial interface. When

is high,

the AD7732 ignores the SCLK and DIN signals and the DOUT

pin goes to the high impedance state. When the

signal is not

used, connect the

pin to DGND.

The

RDY

pin can be polled for high-to-low transition or can

drive the host device interrupt input to indicate that the

AD7732 has finished the selected operation and/or new data

from the AD7732 is available. The host system can also wait a

designated time after a given command is written to the device

before reading. Alternatively, the AD7732 status can be polled.

When the

RDY

pin is not used in the system, it should be left as

an open circuit. (Note that the

RDY

pin is always an active

digital output, i.e., it never goes into a high impedance state.)

All the digital interface inputs are Schmitt-Triggered; therefore,

the AD7732 interface features higher noise immunity and can

be easily isolated from the host system via optocouplers.

Figure 13, Figure 14, and Figure 15 outline some of the possible

host device interfaces: SPI without using the

signal

( ), a DSP interface ( ), and a 2-wire

configuration( ).

Figure 13 Figure 14

Figure 15

SCLK

DIN

DOUT

RDY

RESET

DGND

AD7732

SCK

MOSI

MISO

INT

68HC11

SCLK

DIN

DOUT

RESET

DGND

AD7732

P3.1/TXD

P3.0/RXD

8xC51

Figure 13. AD7732 to Host Device Interface, SPI

Figure 15. AD7732 to Host Device Interface, 2-Wire Configuration

SCLK

DIN

DOUT

RDY

RESET

AD7732

SCLK

INT

TFS

RFS

ADSP-2105

Figure 14. AD7732 to Host Device Interface, DSP

AD7732

Rev. A | Page 23 of 32

Reset

The AD7732 can be reset by the

RESET

pin or by writing a reset

sequence to the AD7732 serial interface.

The reset sequence is N × 0 + 32 × 1, which could be the data

sequence 00h + FFh + FFh + FFh + FFh in a byte-oriented

interface. The AD7732 also features a power-on reset with a

trip point of 2 V and goes to the defined default state after

power-on.

It is the system designer’s responsibility to prevent an unwanted

write operation to the AD7732. The unwanted write operation

could happen when a spurious clock appears on the SCLK while

the

pin is low. It should be noted that on system power-on, if

the AD7732 interface signals are floating or undefined, the part

can be inadvertently configured into an unknown state. This

could be easily overcome by initiating either a hardware reset

event or a 32 ones reset sequence as the first step in the system

configuration.

Access the AD7732 Registers

All communications to the part start with a write operation to

the communications register followed by either reading or

writing the addressed register.

In a simultaneous read-write interface (such as SPI), write 0 to

the AD7732 while reading data.

Figure 16 shows the AD7732 interface read sequence for the

ADC status register.

DIN

SCLK

DOUT

WRITE

COMMUNICATIONS

READ

ADC STATUS

Figure 16. Serial Interface Signals—Registers Access

Single Conversion and Reading Data

When the mode register is being written, the ADC status byte is

cleared and the

RDY

pin goes high, regardless of its previous

state. When the single conversion command is written to the

mode register, the ADC starts the conversion on the channel

selected by the address of the mode register. After the

conversion is completed, the data register is updated, the mode

and the

RDY

pin goes low. The RDY bit is reset and the

RDY

pin returns high when the relevant channel data register is

being read.

Figure 17 shows the digital interface signals executing a single

conversion on Channel 0, waiting for the

RDY

pin to go low,

and reading the Channel 0 data register.

DIN

SCLK

DOUT

WRITE

COMMUNICATIONS

WRITE

MODE

RDY

CONVERSION TIME READ DATA REGISTER

38h

40h 48h (00h) (00h)

DATA DATA

WRITE

COMMUNICATIONS

Figure 17. Serial Interface Signals—Single Conversion Command and 16-Bits Data Reading

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33

AD7732BRUZ

Mfr. #:

Buy AD7732BRUZ

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 2Ch+/-10V InputRange 24-Bit

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AD7732BRUZ

AD7732BRUZ

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