AD7732BRUZ Datasheet AD7732BRUZ, AD7732BRUZ-REEL, AD7732BRUZ-REEL7 | P4-P6

AD7732

Rev. A | Page 3 of 32

AD7732—SPECIFICATIONS

Table 1. (–40°C to +105°C; AV

= 5 V ± 5%; DV

= 2.7 V to 3.6 V, or 5 V ± 5%; BIAS (all), REFIN(+) = 2.5 V;

REFIN(–) = AGND; RA, RB, RC, RD open circuit; AIN Range = ±10 V; f

MCLKIN

= 6.144 MHz; unless otherwise noted.)

Parameter Min Typ Max Unit Test Conditions/Comments

ADC PERFORMANCE

CHOPPING ENABLED

Conversion Time Rate 372 12190 Hz Configure via Conv. Time Register

No Missing Codes

1, 2

24 Bits FW ≥ 6 (Conversion Time ≥ 165 μs)

Output Noise See Table 4

Resolution

See Table 5

and Table 6

Integral Nonlinearity (INL)

1, 2, 3

±0.0003 ±0.0015 % of FSR f

MCLKIN

= 2.5 MHz, V

= 0 V

Integral Nonlinearity (INL)

2, 3

±0.0010 ±0.0030 % of FSR f

MCLKIN

= 6.144 MHz, V

= 0 V

Offset Error (Unipolar, Bipolar)

±13 mV Before Calibration

Offset Drift vs. Temperature

±2.5 μV/°C

Gain Error

±0.7 % Before Calibration

Gain Drift vs. Temperature

±3.2 ppm of FS/°C

Positive Full-Scale Error

±0.7 % of FSR Before Calibration

Positive Full-Scale Drift vs. Temp.

±3 ppm of FS/°C

Bipolar Negative Full-Scale Error

±0.0060 % of FSR After Calibration

Common-Mode Rejection 50 65 dB At DC

Power Supply Sensitivity ±4 ±10 LSB

At DC, AIN = 7 V, AV

= 5 V ± 5%

Channel-to-Channel Isolation 110 dB At DC, Maximum ±16.5 V AIN Voltage

ADC PERFORMANCE

CHOPPING DISABLED

Conversion Time Rate 737 15437 Hz Configure via Conv. Time Register

No Missing Codes

1, 2

24 Bits FW ≥ 8 (Conversion Time ≥ 117 μs)

Output Noise See Table 7

Resolution

See Table 8

and Table 9

Integral Nonlinearity (INL)

2, 3

±0.0015 % of FSR

Offset Error (Unipolar, Bipolar)

±10 mV Before Calibration

Offset Drift vs. Temperature ±25 μV/°C

Gain Error

±0.5 % Before Calibration

Gain Drift vs. Temperature ±5.3 ppm of FS/°C

Positive Full-Scale Error

±0.5 % of FSR Before Calibration

Positive Full-Scale Drift vs. Temp. ±4 ppm of FS/°C

Bipolar Negative Full-Scale Error

±0.0060 % of FSR After Calibration

Common-Mode Rejection 55 dB At DC

Power Supply Sensitivity ±4 LSB

At DC, AIN = 7 V, AV

= 5 V ± 5%

Channel-to-Channel Isolation 110 dB At DC, Maximum ±16.5 V AIN Voltage

ANALOG INPUTS

Analog Input Differential Voltage

±10 V Range

±10

0 V to +10 V Range 0 to +10 V

±5 V Range

±5

0 V to +5 V Range 0 to +5 V

AIN Absolute Voltage

1, 2, 8

–16.5 +16.5 V

BIAS Voltage

0 2.5 AV

RA, RB, RC, RD Voltage

–10.5 +20 V

AIN Impedance

1, 9

100 124 kΩ

AIN Pin Impedance

1, 9

87.5 108.5 kΩ

BIAS Pin Impedance

1, 9

12.5 15.5

kΩ

AD7732

Rev. A | Page 4 of 32

Parameter Min Typ Max Unit Test Conditions/Comments

RA, RB, RC, RD Pin Impedance

1, 9

25 31

kΩ

Input Resistor Matching 0.2 %

Input Resistor Temp. Coefficient –30 ppm/°C

REFERENCE INPUTS

REFIN(+) to REFIN(–) Voltage

1, 10

2.475 2.5 2.525 V

NOREF Trigger Voltage 0.5 V NOREF Bit in Channel Status Register

REFIN(+), REFIN(–)

Common-Mode Voltage

0 AV

Reference Input DC Current

400 μA

SYSTEM CALIBRATION

1, 12

Full-Scale Calibration Limit

+1.05 × FS

Zero-Scale Calibration Limit

–1.05 × FS

Input Span

0.8 × FS

2.1 × FS

LOGIC INPUTS

Input Current

±1

μA

Input Current CS

±10

μA

CS = DV

–40 μA

= DGND, Internal Pull-Up Resistor

Input Capacitance 5 pF

T+

1.4 2 V DV

= 5 V

T–

0.8 1.4 V DV

= 5 V

T+

– V

T–

0.3 0.85 V DV

= 5 V

T+

0.95 2 V DV

= 3 V

T–

0.4 1.1 V DV

= 3 V

T+

– V

T–

0.3 0.85 V DV

= 3 V

MCLK IN ONLY

Input Current

±10

μA

Input Capacitance 5 pF

INL

Input Low Voltage 0.8 V DV

= 5 V

INH

Input High Voltage 3.5 V DV

= 5 V

INL

Input Low Voltage 0.4 V DV

= 3 V

INH

Input High Voltage 2.5 V DV

= 3 V

LOGIC OUTPUTS

Output Low Voltage 0.4 V I

SINK

= 800 μA, DV

= 5 V

Output High Voltage 4.0 V I

SOURCE

= 200 μA, DV

= 5 V

Output Low Voltage 0.4 V I

SINK

= 100 μA, DV

= 3 V

Output High Voltage DV

– 0.6 V I

SOURCE

= 100 μA, DV

= 3 V

Floating State Leakage Current

±1

μA

Floating State Leakage Capacitance 3 pF

P0, P1 INPUTS/OUTPUTS Levels Referenced to Analog Supplies

Input Current

±10

μA

INL

Input Low Voltage 0.8 V AV

= 5 V

INH

Input High Voltage 3.5 V AV

= 5 V

Output Low Voltage 0.4 V I

SINK

= 7 mA, See Abs. Max. Ratings

Output High Voltage 4.0 V I

SOURCE

= 200 μA, AV

= 5 V

POWER REQUIREMENTS

–AGND Voltage 4.75 5.25 V

–DGND Voltage 4.75 5.25 V

2.70 3.60 V

Current (Normal Mode) 13.5 15.9 mA AV

= 5 V

Current (Normal Mode)

2.8 3.1 mA DV

= 5 V

Current (Normal Mode)

1.0 1.5 mA DV

= 3 V

AD7732

Rev. A | Page 5 of 32

Parameter Min Typ Max Unit Test Conditions/Comments

Power Dissipation (Normal Mode)

85 100 mW

+DV

Current (Standby Mode)

140 μA

Power Dissipation (Standby Mode)

750 μW

Specifications are not production tested but guaranteed by design and/or characterization data at initial product release.

See Typical Performance Characteristics.

= Common-Mode Voltage = 0 V.

Specifications before calibration. Channel system calibration reduces these errors to the order of the noise.

Applies after the zero-scale and full-scale calibration. The negative full-scale error represents the remaining error after removing the offset and gain error.

ADC zero-scale self-calibration reduces this error to ±10 mV. Channel zero-scale system calibration reduces this error to the order of the noise.

For specified performance. The output data span corresponds to the specified nominal input voltage range. The ADC is functional outside the nominal input voltage

range, but the performance might degrade. Outside the nominal input voltage range, the OVR bit in the channel status register is set and the channel data register

value depends on the CLAMP bit in the mode register. See the register and circuit descriptions for more details.

The AIN absolute voltage of ±16.5 V applies for a nominal VBIAS voltage of +2.5 V. By configuring the BIAS and RA to RD pins differently, the part will work with higher

AIN absolute voltages as long as the internal voltage seen by the multiplexer and the input buffer is within 200 mV to AV

– 300 mV. Absolute voltage for the AIN,

BIAS, and RA to RD pins must never exceed the values specified in the Absolute Maximum Ratings.

Pin impedance is from the pin to the internal node. In normal circuit configuration, the analog input total impedance is typically 108.5 kΩ + 15.5 kΩ = 124 kΩ.

For specified performance. Part is functional with lower V

REF

Dynamic current charging the sigma-delta modulator input switching capacitor.

Outside the specified calibration range, calibration is possible but the performance may degrade.

These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load.

With external MCLK, MCLKOUT is disabled (the CLKDIS bit is set in the mode register).

External MCLKIN = 0 V or DV

, Digital Inputs = 0 V or DV

, and P0 and P1 = 0 V or AV

DD.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33

AD7732BRUZ

Mfr. #:

Buy AD7732BRUZ

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 2Ch+/-10V InputRange 24-Bit

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AD7732BRUZ

AD7732BRUZ

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