BTS736L2 Datasheet BTS736L2 | P1-P3

PROFET

®

BTS 736 L2

Semiconductor Group 1 of 14 2003-Oct-01

Smart High-Side Power Switch

Two Channels: 2 x 40mΩ

Status Feedback

Product Summary Package

Operating Voltage V

bb(on)

4.75...41V

Active channels one two parallel

On-state Resistance R

ON

40mΩ 20mΩ

Nominal load current I

L(NOM)

4.8A 7.3A

Current limitation I

L(SCr)

30A 30A

General Description

• N channel vertical power MOSFET with charge pump, ground referenced CMOS compatible input and

diagnostic feedback, monolithically integrated in Smart SIPMOS



technology.

• Providing embedded protective functions

Applications

• µC compatible high-side power switch with diagnostic feedback for 5V, 12V and 24V grounded loads

• All types of resistive, inductive and capacitve loads

• Most suitable for loads with high inrush currents, so as lamps

• Replaces electromechanical relays, fuses and discrete circuits

Basic Functions

• Very low standby current

• CMOS compatible input

• Fast demagnetization of inductive loads

• Stable behaviour at undervoltage

• Wide operating voltage range

• Logic ground independent from load ground

Protection Functions

• Short circuit protection

• Overload protection

• Current limitation

• Thermal shutdown

• Overvoltage protection (including load dump) with external

resistor

• Reverse battery protection with external resistor

• Loss of ground and loss of V

bb

protection

• Electrostatic discharge protection (ESD)

Diagnostic Function

• Diagnostic feedback with open drain output

• Open load detection in ON-state

• Feedback of thermal shutdown in ON-state

Block Diagram

P-DSO-20-9

Vbb

Logic

Channel

1

Logic

Channel

2

IN1

ST1

IN2

ST2

GND

Load 1

Load 2

PROFET

OUT 1

OUT 2

BTS 736 L2

Semiconductor Group 2 2003-Oct-01

Functional diagram

Pin Definitions and Functions

Pin Symbol Function

1,10,

11,12,

15,16,

19,20

V

bb

Positive power supply voltage. Design the

wiring for the simultaneous max. short circuit

currents from channel 1 to 2 and also for low

thermal resistance

3 IN1 Input 1,2, activates channel 1,2 in case of

7 IN2 logic high signal

17,18 OUT1 Output 1,2, protected high-side power output

13,14 OUT2 of channel 1,2. Design the wiring for the max.

short circuit current

4 ST1 Diagnostic feedback 1,2 of channel 1,2,

8 ST2 open drain, low on failure

2 GND1 Ground 1 of chip 1 (channel 1)

6 GND2 Ground 2 of chip 2 (channel 2)

5,9 N.C. Not Connected

Pin configuration

(top view)

V

bb

1 • 20 V

bb

GND1 2 19 V

bb

IN1 3 18 OUT1

ST1 4 17 OUT1

N.C. 5 16 V

bb

GND2 6 15 V

bb

IN2 7 14 OUT2

ST2 8 13 OUT2

N.C. 9 12 V

bb

V

bb

10 11 V

bb

OUT1

overvoltage

p

rotection

logic

internal

volta

g

e su

pp

l

y

ESD

temperature

sensor

clamp for

inductive load

gate

control

+

charge

pump

current limit

Open load

detection

ST1

VBB

LOAD

IN1

PROFET

GND1

Control and protection circuit

of

channel 2

IN2

ST2

OUT2

Channel 1

GND2

BTS 736 L2

Semiconductor Group 3 2003-Oct-01

Maximum Ratings at T

j

= 25°C unless otherwise specified

Parameter Symbol Values Unit

Supply voltage (overvoltage protection see page 4) V

bb

43 V

Supply voltage for full short circuit protection

T

j,start

= -40 ...+150°C

V

bb

24 V

Load current (Short-circuit current, see page 5) I

L

self-limited A

Load dump protection

1)

V

LoadDump

= V

A

+ V

s

, V

A

= 13.5 V

R

I

2)

= 2 Ω, t

d

= 200 ms; IN = low or high,

each channel loaded with R

L

= 9.0 Ω,

V

Load dump

3

)

60 V

Operating temperature range

Storage temperature range

T

j

T

stg

-40 ...+150

-55 ...+150

°C

Power dissipation (DC)

4)

T

a

= 25°C:

(all channels active)

T

a

= 85°C:

P

tot

3.8

2.0

W

Maximal switchable inductance, single pulse

V

bb

= 12V, T

j,start

= 150°C

4)

,

I

L

= 4.0 A, E

AS

= 296 mJ, 0 Ω one channel:

I

L

= 6.0 A, E

AS

= 631 mJ, 0 Ω two parallel channels:

see diagrams on page 9

Z

L

19.0

17.5

mH

Electrostatic discharge capability (ESD) IN:

(Human Body Model) ST:

out to all other pins shorted:

acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993

R=1.5kΩ; C=100pF

V

ESD

1.0

4.0

8.0

kV

Input voltage (DC) V

IN

-10 ... +16 V

Current through input pin (DC)

Current through status pin (DC)

see internal circuit diagram page 8

I

IN

I

ST

±2.0

±5.0

mA

Thermal Characteristics

Parameter and Conditions Symbol Values Unit

min typ Max

Thermal resistance

junction - soldering point

4),5)

each channel: R

thjs

-- -- 12

K/W

junction - ambient

4)

one channel active:

all channels active:

R

thja

--

40

33

--

1)

Supply voltages higher than V

bb(AZ)

require an external current limit for the GND and status pins (a 150Ω

resistor for the GND connection is recommended.

2)

R

I

= internal resistance of the load dump test pulse generator

3)

V

Load dump

is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839

4)

Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm

2

(one layer, 70µm thick) copper area for V

bb

connection. PCB is vertical without blown air. See page 14

5)

Soldering point: upper side of solder edge of device pin 15. See page 14

BTS736L2

BTS736L2

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