Notes:
1. Output IC power dissipation is derated linearly above 80 °C from 580 mW to 260 mW at 105 °C.
2. This supply is optional. Required only when negative gate drive is implemented.
3. Maximum 500 ns pulse width if peak V
DESAT
> 10 V.
4. Maximum pulse width = 1 ms, maximum duty cycle = 1%.
5. In most applications V
CC1
will be powered up rst (before V
CC2
) and powered down last (after V
CC2
). This is desirable for maintaining control of the
IGBT gate. In applications where V
CC2
is powered up rst, it is important to ensure that input remains low until V
CC1
reaches the proper operating
voltage to avoid any momentary instability at the output during V
CC1
ramp-up or ramp-down.
6. 15 V is the recommended minimum operating positive supply voltage (V
CC2
- V
E
) to ensure adequate margin in excess of the maximum V
UVLO+
threshold of 13.5 V.
7. If DC-DC controller is not used for powering output IC.
8. For High Level Output Voltage testing, V
OH
is measured with a DC load current. When driving capacitive loads, V
OH
will approach V
CC
as I
OH
approaches zero.
9. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%.
10. Once V
OUT
of the ACPL-302J is allowed to go high (V
CC2
- V
E
> V
UVLO
), the DESAT detection feature of the ACPL-302J will be the primary source of
IGBT protection. UVLO is needed to ensure DESAT is functional. Once V
CC2
exceeds V
UVLO+
threshold, DESAT will remain functional until V
CC2
is
below V
UVLO-
threshold. Thus, the DESAT detection and UVLO features of the ACPL-302J work in conjunction to ensure constant IGBT protection.
11. t
PLH
is dened as propagation delay from 50% of LED input I
F
to 50% of High level output.
12. t
PHL
is dened as propagation delay from 50% of LED input I
F
to 50% of Low level output.
13. Pulse Width Distortion (PWD) is dened as (t
PHL
– t
PLH
) of any given unit.
14. As measured from I
F
to V
O
.
15. Dead Time Distortion (DTD) is dened as (t
PLH
- t
PHL
) between any two ACPL-302J parts under the same test conditions.
16. Common mode transient immunity in the high state is the maximum tolerable dV
CM
/dt of the common mode pulse, V
CM
, to assure that the output
will remain in the high state (i.e., V
O
> 15 V). A 330 pF and a 10 kΩ pull-up resistor is needed in fault and UVLO detection mode.
17. Common mode transient immunity in the low state is the maximum tolerable dV
CM
/dt of the common mode pulse, V
CM
, to assure that the output
will remain in a low state (i.e., V
O
< 1.0 V). A 330 pF and a 10 kΩ pull-up resistor is needed in fault and UVLO detection mode.
18. This is the “increasing” (i.e. turn-on or “positive going” direction) of V
CC2
- V
E
.
19. This is the “decreasing” (i.e. turn-o or “negative going” direction) of V
CC2
- V
E
.
20. The delay time when V
CC2
exceeds UVLO+ threshold to UVLO positive-going edge.
21. The delay time when V
CC2
falls below UVLO- threshold to UVLO negative-going edge.
22. The delay time when V
CC2
exceeds UVLO+ threshold to 50% of High level output.
23. The delay time when V
CC2
falls below UVLO- threshold to 50% of Low level output.
24. The delay time for ACPL-302J to respond to a DESAT fault condition without any external DESAT capacitor.
25. The amount of time from when DESAT threshold is exceeded to 90% of V
GATE
at mentioned test conditions.
26. The amount of time from when DESAT threshold is exceeded to 10% of V
GATE
at mentioned test conditions.
27. The amount of time from when DESAT threshold is exceeded to FAULT output Low – 50% of V
CC1
voltage.
28. The amount of time when DESAT threshold is exceeded, Output is mute to LED input.
29. The amount of time when DESAT Mute time is expired, LED input must be kept Low for Fault status to return to High.
30. In accordance with UL1577, each optocoupler is proof-tested by applying an insulation test voltage ≥ 6000 V
RMS
for 1 second.
31. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage
rating. For the continuous voltage rating, refer to your equipment level safety specication or IEC/EN/DIN EN 60747-5-5 Insulation Characteristics
Table.
32. Device considered a two-terminal device: pins 1 - 8 shorted together and pins 9 - 16 shorted together.
33. Max 34V, 10 pulses, 400ms pulse width, 60s intervals.
PCB top side
PCB bottom side
VEE1
VEE1
VEE2
40 mm
60 mm
VEE1
VEE2
40 mm
60 mm
Thermal Characteristics are based on the ground planes layout of the evaluation PCB.
Figure 7. PCB Layout of evaluation board used for thermal characterization
13
