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LTC3407AEDD-2#TRPBF

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LTC3407A-2
10
3407a2f
Power-On Reset
The POR pin is an open-drain output which pulls low when
either regulator is out of regulation. When both output
voltages are within ±8.5% of regulation, a timer is started
which releases POR after 2
16
clock cycles (about 29ms in
pulse skipping mode). This delay can be significantly
longer in Burst Mode operation with low load currents,
since the clock cycles only occur during a burst and there
could be milliseconds of time between bursts. This can be
bypassed by tying the POR output to the MODE/SYNC
input, to force pulse skipping mode during a reset. In
addition, if the output voltage faults during Burst Mode
sleep, POR could have a slight delay for an undervoltage
output condition and may not respond to an overvoltage
output. This can be avoided by using pulse skipping mode
instead. When either channel is shut down, the POR
output is pulled low, since one or both of the channels are
not in regulation.
Mode Selection & Frequency Synchronization
The MODE/SYNC pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connect-
ing this pin to V
IN
enables Burst Mode operation, which
provides the best low current efficiency at the cost of a
higher output voltage ripple. When this pin is connected to
ground, pulse skipping operation is selected which pro-
vides the lowest output ripple, at the cost of low current
efficiency.
The LTC3407A-2 can also be synchronized to another
LTC3407A-2 by the MODE/SYNC pin. During synchroni-
zation, the mode is set to pulse skipping and the top switch
turn-on is synchronized to the rising edge of the external
clock.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to ΔI
LOAD
• ESR, where ESR is the effective series
resistance of C
OUT
. ΔI
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used by
the regulator to return V
OUT
to its steady-state value. During
APPLICATIO S I FOR ATIO
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At worst, the ringing at the input can be large enough to
damage the part.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough to
support the load. The time required for the feedback loop
to respond is dependent on the compensation and the
output capacitor size. Typically, 3-4 cycles are required to
respond to a load step, but only in the first cycle does the
output drop linearly. The output droop, V
DROOP
, is usually
about 3 times the linear drop of the first cycle. Thus, a good
place to start is with the output capacitor size of approxi-
mately:
C
I
fV
OUT
OUT
O DROOP
≈
Δ
3
•
More capacitance may be required depending on the duty
cycle and load step requirements.
In most applications, the input capacitor is merely re-
quired to supply high frequency bypassing, since the
impedance to the supply is very low. A 10μF ceramic
capacitor is usually enough for these conditions.
Setting the Output Voltage
The LTC3407A-2 develops a 0.6V reference voltage be-
tween the feedback pin, V
FB
, and ground as shown in
Figure 1. The output voltage is set by a resistive divider
according to the following formula:
VV
R
R
OUT
=+
⎛
⎝
⎜
⎞
⎠
⎟
06 1
2
1
.
Keeping the current small (<5μA) in these resistors maxi-
mizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.
To improve the frequency response, a feed-forward ca-
pacitor C
F
may also be used. Great care should be taken to
route the V
FB
line away from noise sources, such as the
inductor or the SW line.
LTC3407A-2
11
3407a2f
For approximately a 1ms ramp time, use R
SS
= 4.7MΩ and
C
SS
= 680pF at V
IN
= 3.3V.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% - (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, 4 main sources usually account for most of the
losses in LTC3407A-2 circuits: 1)V
IN
quiescent current, 2)
switching losses, 3) I
2
R losses, 4) other losses.
1) The V
IN
current is the DC supply current given in the
Electrical Characteristics which excludes MOSFET driver
and control currents. V
IN
current results in a small (<0.1%)
loss that increases with V
IN
, even at no load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
from switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from V
IN
to
ground. The resulting dQ/dt is a current out of V
IN
that is
typically much larger than the DC bias current. In continu-
ous mode, I
GATECHG
= f
O
(Q
T
+ Q
B
), where Q
T
and Q
B
are the
gate charges of the internal top and bottom MOSFET
switches. The gate charge losses are proportional to V
IN
and thus their effects will be more pronounced at higher
supply voltages.
3) I
2
R losses are calculated from the DC resistances of the
internal switches, R
SW
, and external inductor, R
L
. In
continuous mode, the average output current flows through
inductor L, but is “chopped” between the internal top and
bottom switches. Thus, the series resistance looking into
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Hot Swap is a registered trademark of Linear Technology Corporation.
this recovery time, V
OUT
can be monitored for overshoot
or ringing that would indicate a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second-
order overshoot/DC ratio cannot be used to determine
phase margin. In addition, a feed-forward capacitor can be
added to improve the high frequency response, as shown
in Figure 1. Capacitors C1 and C2 provide phase lead by
creating high frequency zeros with R2 and R4 respec-
tively, which improve the phase margin.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance. For a detailed
explanation of optimizing the compensation components,
including a review of control loop theory, refer to Applica-
tion Note 76.
In some applications, a more severe transient can be
caused by switching in loads with large (>1μF) input
capacitors. The discharged input capacitors are effectively
put in parallel with C
OUT
, causing a rapid drop in V
OUT
. No
regulator can deliver enough current to prevent this prob-
lem, if the switch connecting the load has low resistance
and is driven quickly. The solution is to limit the turn-on
speed of the load switch driver. A Hot Swap
TM
controller is
designed specifically for this purpose and usually incorpo-
rates current limiting, short-circuit protection, and soft-
starting.
Soft-Start
The RUN/SS pins provide a means to separately run or
shut down the two regulators. In addition, they can option-
ally be used to externally control the rate at which each
regulator starts up and shuts down. Pulling the RUN/SS1
pin below 1V shuts down regulator 1 on the LTC3407A-2.
Forcing this pin to V
IN
enables regulator 1. In order to
control the rate at which each regulator turns on and off,
connect a resistor and capacitor to the RUN/SS pins as
shown in Figure 1. The soft-start duration can be calcu-
lated by using the following formula:
tRCIn
V
V
s
SS SS SS
IN
IN
=
−
−
⎛
⎝
⎜
⎞
⎠
⎟
1
16.
()
LTC3407A-2
12
3407a2f
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
RISE
+ T
AMBIENT
As an example, consider the case when the LTC3407A-2
is in dropout on both channels at an input voltage of 2.7V
with a load current of 800mA and an ambient temperature
of 70°C. From the Typical Performance Characteristics
graph of Switch Resistance, the R
DS(ON)
resistance of the
main switch is 0.425Ω. Therefore, power dissipated by
each channel is:
P
D
= I
2
• R
DS(ON)
= 272mW
The MS package junction-to-ambient thermal resistance,
θ
JA
, is 45°C/W. Therefore, the junction temperature of the
regulator operating in a 70°C ambient temperature is
approximately:
T
J
= 2 • 0.272 • 45 + 70 = 94.5°C
which is below the absolute maximum junction tempera-
ture of 125°C.
Design Example
As a design example, consider using the LTC3407A-2 in a
portable application with a Li-Ion battery. The battery
provides a V
IN
= 2.8V to 4.2V. The load requires a maxi-
mum of 800mA in active mode and 2mA in standby mode.
The output voltage is V
OUT
= 2.5V. Since the load still
needs power in standby, Burst Mode operation is selected
for good low load efficiency.
First, calculate the inductor value for about 30% ripple
current at maximum V
IN
:
L
V
MHz mA
V
V
H=
⎛
⎝
⎜
⎞
⎠
⎟
= μ
25
2 25 360
1
25
42
125
.
.•
•–
.
.
.
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the SW pin is a function of both top and bottom MOSFET
R
DS(ON)
and the duty cycle (D) as follows:
R
SW
= (R
DS(ON)TOP
)(D) + (R
DS(ON)BOT
)(1 – D)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
2
R losses:
I
2
R losses = I
OUT
2
(R
SW
+ R
L
)
4) Other ‘hidden’ losses such as copper trace and internal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important to
include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that C
IN
has adequate
charge storage and very low ESR at the switching fre-
quency. Other losses including diode conduction losses
during dead-time and inductor core losses generally ac-
count for less than 2% total additional loss.
Thermal Considerations
In a majority of applications, the LTC3407A-2 does not
dissipate much heat due to its high efficiency. However, in
applications where the LTC3407A-2 is running at high
ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will be turned off and the SW node
will become high impedance.
To prevent the LTC3407A-2 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T
RISE
= P
D
• θ
JA
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LTC3407AEDD-2#TRPBF

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Buy LTC3407AEDD-2#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual 800mA, 2.25MHz Synchronous Step-Down with Improved BurstMode
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