LTC3407A-2
13
3407a2f
APPLICATIO S I FOR ATIO
WUU
U
LTC3407A-2. These items are also illustrated graphically
in the layout diagram of Figure 2. Check the following in
your layout:
1. Does the capacitor C
IN
connect to the power V
IN
(Pin 3)
and GND (exposed pad) as closely as possible? This
capacitor provides the AC current to the internal power
MOSFETs and their drivers.
2. Are C
OUT
and L1 closely connected? The (–) plate of
C
OUT
returns current to GND and the (–) plate of C
IN
.
3. The resistor divider formed by R1 and R2 must be
connected between the (+) plate of C
OUT
and a ground
sense line terminated near GND (exposed pad). The feed-
back signals V
FB1
and V
FB2
should be routed away from
noisy components and traces, such as the SW lines (Pins
4 and 7), and their traces should be minimized.
4. Keep sensitive components away from the SW pins. The
input capacitor C
IN
and the resistors R1 to R4 should be
routed away from the SW traces and the inductors.
5. A ground plane is preferred, but if not available keep the
signal and power grounds segregated with small signal
components returning to the GND pin at one point.
Addtionally the two grounds should not share the high
current paths of C
IN
or C
OUT
.
6. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise of
power components. These copper areas should be con-
nected to V
IN
or GND.
Figure 2. LTC3407A-2 Layout Diagram (See Board Layout Checklist)
RUN/SS2 V
IN
V
IN
V
OUT2
V
OUT1
RUN/SS1
POR
SW1
V
FB1
GND
V
FB2
SW2
MODE/SYNC
LTC3407A-2
C
IN
C4C5
L1
L2
R4 R2
R1
R3
C
OUT2
C
OUT1
3407A2 F02
BOLD LINES INDICATE HIGH CURRENT PATHS
Choosing the next highest standardized inductor value of
2.2μH, results in a maximum ripple current of:
Δ =
μ
−
⎛
⎝
⎜
⎞
⎠
⎟
=I
V
MHz H
V
V
m
L
25
225 22
1
25
42
204
.
.•.
•
.
.
AA
For cost reasons, a ceramic capacitor will be used. C
OUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
C
mA
MHz V
F
OUT
≈ = μ25
800
225 5 25
71.
.•(%•.)
.
The closest standard value is 10μF. Since the output
impedance of a Li-Ion battery is very low, C
IN
is typically
10μF.
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2μA with the 0.6V feedback voltage makes R1~300k. A
close standard 1% resistor is 280k, and R2 is then 887k.
The POR pin is a common drain output and requires a pull-
up resistor. A 100k resistor is used for adequate speed.
Figure 3 shows the complete schematic for this design
example. The specific passive components chosen allow
for a 1mm height power supply that maintains a high
efficiency across load.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
