13
FN8126.3
September 23, 2015
NOTES:
1. V
IL
min. and V
IH
max. are for reference only and are not tested.
2. This parameter is periodically sampled and not 100% tested.
3. SCK frequency measured from V
CC
x 0.1/V
CC
x 0.9
Absolute Maximum Ratings Recommended Operating Conditions
Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on any pin with
respect to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +7V
D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300°C
Temperature:
Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage:
-2.7, -2.7A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Blank, -4.5A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
DC Electrical Specifications (Over the recommended operating conditions unless otherwise specified.)
SYMBOL PARAMETER TEST CONDITIONS/COMMENTS
LIMITS
UNITMIN TYP
(2)
MAX
I
CC1
V
CC
Write Current (Active) SCK = 3.3MHz
(3)
; SO, RESET, RESET = Open 3 mA
I
CC2
V
CC
Read Current (Active) SCK = 3.3MHz
(3)
; SI = V
SS
, RESET, RESET =
Open
2mA
I
SB1
V
CC
Standby Current WDT = OFF CS = V
CC
, SCK, SI = V
SS
,
V
CC
=5.5V 10 µA
I
SB2
V
CC
Standby Current WDT = ON CS = V
CC
, SCK, SI = V
SS
,
V
CC
=5.5V 50 µA
I
LI
Input Leakage Current SCK, SI, WP = V
SS
to V
CC
0.110µA
I
LO
Output Leakage Current SO, RESET, RESET = V
SS
to V
CC
0.1 10 µA
V
IL
(1)
Input LOW Voltage SCK, SI, WP, CS -0.5 V
CC
x 0.3 V
V
IH
(1)
Input HIGH Voltage SCK, SI, WP, CS V
CC
x 0.7 V
CC
+ 0.5 V
V
OL
Output LOW Voltage (SO) I
OL
= 2mA @ V
CC
= 2.7V
I
OL
= 0.5mA @ V
CC
= 1.8V
0.4 V
V
OH1
Output HIGH Voltage (SO) V
CC
> 3.3V, I
OH
= –1.0mA V
CC
- 0.8 V
V
OH2
Output HIGH Voltage (SO) 2V < V
CC
3.3V, I
OH
= –0.4mA V
CC
- 0.4 V
V
OH3
Output HIGH Voltage (SO) V
CC
2V, I
OH
= –0.25mA V
CC
- 0.2 V
V
OLRS
Output LOW Voltage (RESET,
RESET)
I
OL
= 1mA 0.4 V
Capacitance T
A
= +25°C, f = 1MHz, V
CC
= 5V
SYMBOL TEST CONDITIONS MAX UNIT
C
OUT
(2)
Output Capacitance (SO, RESET, RESET) V
OUT
= 0V 8 pF
C
IN
(2)
Input Capacitance (SCK, SI, CS, WP)V
IN
= 0V 6 pF
X5043, X5045
14
FN8126.3
September 23, 2015
Equivalent A.C. Load Circuit at 5V V
CC
NOTES:
4. This parameter is periodically sampled and not 100% tested.
5. t
WC
is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
5V
Output
30pF
5V
4.6k
RESET/RESET
30pF
1.64k
1.64k
A.C. Test Conditions
Input pulse levels V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times 10ns
Input and output timing level V
CC
x 0.5
AC Electrical Specifications (Over recommended operating conditions, unless otherwise specified)
SYMBOL PARAMETER
2.7V–5.5V
UNITMIN MAX
DATA INPUT TIMING
f
SCK
Clock Frequency 0 3.3 MHz
t
CYC
Cycle Time 300 ns
t
LEAD
CS Lead Time 150 ns
t
LAG
CS Lag Time 150 ns
t
WH
Clock HIGH Time 130 ns
t
WL
Clock LOW Time 130 ns
t
SU
Data Setup Time 30 ns
t
H
Data Hold Time 30 ns
t
RI
(4)
Input Rise Time s
t
FI
(4)
Input Fall Time s
t
CS
CS Deselect Time 100 ns
t
WC
(5)
Write Cycle Time 10 ms
Data Output Timing
SYMBOL PARAMETER
2.7–5.5V
UNIT MIN MAX
f
SCK
Clock Frequency 0 3.3 MHz
t
DIS
Output Disable Time 150 ns
t
V
Output Valid from Clock Low 120 ns
t
HO
Output Hold Time 0 ns
t
RO
(4)
Output Rise Time 50 ns
t
FO
(4)
Output Fall Time 50 ns
X5043, X5045
15
FN8126.3
September 23, 2015
Serial Output Timing
Serial Input Timing
Symbol Table
SCK
CS
SO
SI
MSB Out MSB–1 Out LSB Out
ADDR
LSB IN
t
CYC
t
V
t
HO
t
WL
t
WH
t
DIS
t
LAG
SCK
CS
SI
SO
MSB In
t
SU
t
RI
t
LAG
t
LEAD
t
H
LSB In
t
CS
tFI
High Impedance
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
X5043, X5045

X5043S8IZ-4.5AT1

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Supervisory Circuits CPU SUP/WDT 4K SPI EES LO 8LD 5V+/-10%
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union