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MAX4719EUB+

P1-P3P4-P6P7-P9P10-P11
MAX4719
20
Ω
, 300MHz Bandwidth, Dual SPDT Analog
Switch in UCSP
_______________________________________________________________________________________ 7
Detailed Description
The MAX4719 high-speed, low-voltage, 20Ω R
ON
, dual
SPDT analog switch operates from a single +1.8V to
+5.5V supply. The switch features break-before-make
switching operation and fast switching speeds (t
ON
=
80ns (max), t
OFF
= 40ns (max)).
Applications Information
Digital Control Inputs
The MAX4719 logic inputs accept up to +5.5V regard-
less of supply voltage. For example, with a +3.3V sup-
ply, IN_ can be driven low to GND and high to +5.5V
allowing for mixing of logic levels in a system. Driving
the control logic inputs rail-to-rail minimizes power con-
sumption. For a +3V supply voltage, the logic thresh-
olds are 0.5V (low) and 1.4V (high); for a +5V supply
voltage, the logic thresholds are 0.8V (low) and 2.0V
(high).
Analog Signal Levels
The on-resistance of the MAX4719 changes very little for
analog input signals across the entire supply voltage
range (see the Typical Operating Characteristics). The
switches are bidirectional, so the NO_, NC_, and COM_
pins can be either inputs or outputs.
PIN
UCSP µMAX
NAME FUNCTION
A1 7 NC2
Analog Switch 2—Normally Closed
Terminal
A2 8 IN2
Digital Control Input for Analog
Switch 2
A3 9 COM2
Analog Switch 2—Common
Terminal
A4 10 NO2
Analog Switch 2—Normally Open
Terminal
B1 6 GND Ground
B4 1 V+ Positive-Supply Voltage Input
C1 5 NC1
Analog Switch 1—Normally Closed
Terminal
C2 4 IN1
Digital Control Input for Analog
Switch 1
C3 3 COM1
Analog Switch 1—Common
Terminal
C4 2 NO1
Analog Switch 1—Normally Open
Terminal
Pin Description
TURN-ON/OFF TIME
vs. TEMPERATURE
MAX4719 toc11
TEMPERATURE (°C)
t
ON
/t
OFF
(ns)
603510-15
10
20
40
30
50
60
0
-40 85
t
ON
, V+ = 3.0V t
ON
, V+ = 5.0V
t
OFF
, V+ = 5.0V
t
OFF
, V+ = 3.0V
FREQUENCY RESPONSE
MAX4719 toc12
FREQUENCY (MHz)
ON-LOSS (dB)
10.01
-120
-100
-80
-60
-40
-20
0
20
-140
0.0001 100
V+ = 3V/5V
ON-LOSS
OFF-ISOLATION
CROSSTALK
Typical Operating Characteristics (continued)
(T
A
= +25°C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
MAX4719 toc13
FREQUENCY (Hz)
THD (%)
10k1k100
0.1
10 100k
1
0.01
V+ = 3V
R
L
= 600Ω
Test Circuits/Timing Diagrams
t
r
< 5ns
t
f
< 5ns
50%
V
IL
LOGIC
INPUT
R
L
300Ω
COM_
GND
IN_
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
N_ (
R
L
)
R
L
+ R
ON
V
N_
V
IH
t
OFF
0V
NO_
OR NC_
0.9 x V
0UT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
V+
C
L
35pF
V+
V
OUT
MAX4719
Figure 1. Switching Time
50%
V
IH
V
IL
LOGIC
INPUT
V
OUT
0.9 x V
OUT
t
BBM
LOGIC
INPUT
R
L
300Ω
GND
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_
IN_
NC_
V
OUT
V+
V+
C
L
35pF
V
N_
COM_
MAX4719
Figure 2. Break-Before-Make Interval
MAX4719
Power-Supply Sequencing and
Overvoltage Protection
Caution: Do not exceed the absolute maximum rat-
ings because stresses beyond the listed ratings
may cause permanent damage to the device.
Proper power-supply sequencing is recommended for
all CMOS devices. Always apply V+ before applying
analog signals, especially if the analog signal is not
current-limited.
UCSP Package Considerations
For general UCSP package information and PC layout
considerations, please refer to the Maxim Application
Note (Wafer-Level Chip-Scale Package).
UCSP Reliability
The chip-scale package (UCSP) represents a unique
packaging form factor that may not perform equally to a
packaged product through traditional mechanical relia-
bility tests. UCSP reliability is integrally linked to the
user’s assembly methods, circuit board material, and
usage environment. The user should closely review
these areas when considering use of a UCSP package.
Performance through Operating Life Test and Moisture
Resistance remains uncompromised as it is primarily
determined by the wafer-fabrication process.
Mechanical stress performance is a greater considera-
tion for a UCSP package. UCSPs are attached through
direct solder contact to the user’s PC board, foregoing
the inherent stress relief of a packaged product lead
frame. Solder joint contact integrity must be consid-
ered. Information on Maxim’s qualification plan, test
data, and recommendations are detailed in the UCSP
application note, which can be found on Maxim’s web-
site at www.maxim-ic.com.
Chip Information
TRANSISTOR COUNT: 235
PROCESS: BiCMOS
20
Ω
, 300MHz Bandwidth, Dual SPDT Analog
Switch in UCSP
8 _______________________________________________________________________________________
MAX4719
20
Ω
, 300MHz Bandwidth, Dual SPDT Analog
Switch in UCSP
_______________________________________________________________________________________ 9
V
GEN
GND
COM_
C
L
V
OUT
V+
V
OUT
IN
OFF
ON
OFF
∆V
OUT
Q = (∆V
OUT
)(C
L
)
NC_
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
OFF
ON
OFF
IN
V
IL
TO V
IH
V+
R
GEN
IN_
MAX4719
OR NO_
Figure 3. Charge Injection
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH.
ON-LOSS IS MEASURED BETWEEN COM_ AND "ON" NO_ OR NC_ TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
+5V
V
OUT
V+
IN_
NC1
COM1
NO1
*
V
IN
MAX4719
OFF-ISOLATION = 20log
V
OUT
V
IN
ON-LOSS = 20log
V
OUT
V
IN
CROSSTALK = 20log
V
OUT
V
IN
NETWORK
ANALYZER
50Ω
*FOR CROSSTALK THIS PIN IS NO2.
NC2 AND COM2 ARE OPEN.
50Ω 50Ω
50Ω
MEAS REF
10nF
0V OR V+
50Ω
GND
Figure 4. On-Loss, Off-Isolation, and Crosstalk
CAPACITANCE
METER
NC_ or
NO_
COM_
GND
IN
V
IL
OR
V
IH
10nF
V+
f = 1MHz
V+
MAX4719
Figure 5. Channel Off/On-Capacitance
Test Circuits/Timing Diagrams (continued)
P1-P3P4-P6P7-P9P10-P11

MAX4719EUB+

Mfr. #:
Buy MAX4719EUB+
Manufacturer:
Maxim Integrated
Description:
Analog Switch ICs 20Ohm 300MHz SPDT Analog Switch
Lifecycle:
New from this manufacturer.
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