AD606
REV. B
–3–
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD606JN 0°C to +70°C 16-Lead Plastic DIP N-16
AD606JR 0°C to +70°C 16-Lead Narrow-Body R-16A
SOIC
AD606JR-REEL 0°C to +70°C 13" Tape and Reel R-16A
AD606JR-REEL7 0°C to +70°C 7" Tape and Reel R-16A
AD606-EB Evaluation Board
AD606JCHIPS 0°C to +70°C Die
PIN DESCRIPTION
Plastic DIP (N)
and
Small Outline (R)
Packages
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
INLO INHI
AD606
COMM COMM
ISUM PRUP
ILOG VPOS
BFIN FIL1
VLOG FIL2
OPCM LADJ
LMLO LMHI
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage V
POS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . +9 V
Internal Power Dissipation
2
. . . . . . . . . . . . . . . . . . . 600 mW
Operating Temperature Range . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
16-Lead Plastic DIP Package: θ
JA
= 85°C/W
16-Lead SOIC Package: θ
JA
= 100°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD606 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Function
1 INLO DIFFERENTIAL RF INPUT
–75 dBm to +5 dBm, Inverting, AC Coupled.
2 COMM POWER SUPPLY COMMON
Connect to Ground.
3 ISUM LOG DETECTOR SUMMING NODE
4 ILOG LOG CURRENT OUTPUT
Normally No Connection; 2 µA/dB Output
Current.
5 BFIN BUFFER INPUT
Optionally Used to Realize Low Frequency
Post-Demodulation Filters.
6 VLOG BUFFERED LOG OUTPUT
37.5 mV/dB (100 mV to 4.5 V).
7 OPCM OUTPUT COMMON
Connect to Ground.
8 LMLO DIFFERENTIAL LIMITER OUTPUT
1.2 mA Full-Scale Output Current. Open
Collector Output Must Be “Pulled” Up to
VPOS with R 400 .
9 LMHI DIFFERENTIAL LIMITER OUTPUT
1.2 mA Full-Scale Output Current. Open
Collector Output Must Be “Pulled” Up to
VPOS with R 400 .
10 LADJ LIMITER LEVEL ADJUSTMENT
Optionally Used to Adjust Limiter Output
Current.
11 FIL1 OFFSET LOOP LOW-PASS FILTER
Normally No Connection; a Capacitor Between
FIL1 and FIL2 May Be Added to Lower the
Filter Cutoff Frequency.
12 FIL2 OFFSET LOOP LOW-PASS FILTER
Normally No Connection; See Above.
13 VPOS POSITIVE SUPPLY
Connect to +5 V at 13 mA.
14 PRUP POWER UP
CMOS (5 V) Logical High = Device On
( 65 mW).
CMOS (0 V) Logical Low = Device Off
( 325 µW).
15 COMM POWER SUPPLY COMMON
Connect to Ground.
16 INHI DIFFERENTIAL RF INPUT
–75 dBm to +5 dBm, Noninverting, AC-Coupled.
WARNING!
ESD SENSITIVE DEVICE
AD606
REV. B
–4–
INPUT LEVEL CONVENTIONS
RF logarithmic amplifiers usually have their input specified in
“dBm,” meaning “decibels with respect to 1 mW.” Unfortu-
nately, this is not precise for several reasons.
1. Log amps respond not to power but to voltage. In this re-
spect, it would be less ambiguous to use “dBV” (decibels
referred to 1 V) as the input metric. Also, power is dependent
on the rms (root mean-square) value of the signal, while log
amps are not inherently rms responding.
2. The response of a demodulating log amp depends on the
waveform. Convention assumes that the input is sinusoidal.
However, the AD606 is capable of accurately handling any
input waveform, including ac voltages, pulses and square
waves, Gaussian noise, and so on. See the AD640 data sheet,
which covers the effect of waveform on logarithmic intercept,
for more information.
3. The impedance in which the specified power is measured is
not always stated. In the log amp context it is invariably
assumed to be 50 . Thus, 0 dBm means “1 mW rms in 50 ,”
and corresponds to an rms voltage of
(1 mW × 50 ),
or
224 mV.
Popular convention requires the use of dBm to simplify the
comparison of log amp specifications. Unless otherwise stated,
sinusoidal inputs expressed as dBm in 50 are used to specify
the performance of the AD606 throughout this data sheet. We
will also show the corresponding rms voltages where it helps to
clarify the specification. Noise levels will likewise be given in
dBm; the response to Gaussian noise is 0.5 dB higher than for a
sinusoidal input of the same rms value.
Note that dynamic range, being a simple ratio, is always speci-
fied simply as “dB”, and the slope of the logarithmic transfer
function is correctly specified as “mV/dB,” NOT as “mV/dBm.”
LOGARITHMIC SLOPE AND INTERCEPT
A generalized logarithmic amplifier having an input voltage V
IN
and output voltage V
LOG
must satisfy a transfer function of the
form
VV VV
LOG Y IN X
= log ( / )
10
where, in the case of the AD606, the voltage V
IN
is the differ-
ence between the voltages on pins INHI and INLO, and the
voltage V
LOG
is that measured at the output pin VLOG. V
Y
and
V
X
are fixed voltages that determine the slope and intercept of
the logarithmic amplifier, respectively. These parameters are
inherent in the design of a particular logarithmic amplifier,
although may be adjustable, as in the AD606. When V
IN
= V
X
,
the logarithmic argument is one, hence the logarithm is zero. V
X
is, therefore, called the logarithmic intercept voltage because the
output voltage V
LOG
crosses zero for this input. The slope volt-
age V
Y
is can also be interpreted as the “volts per decade” when
using base-10 logarithms as shown here.
Note carefully that V
LOG
and VLOG in the above paragraph
(and elsewhere in this data sheet) are different. The first is a
voltage; the second is a pin designation.
This equation suggests that the input V
IN
is a dc quantity, and,
if V
X
is positive, that V
IN
must likewise be positive, since the
logarithm of a negative number has no simple meaning. In fact,
in the AD606, the response is independent of the sign of V
IN
because of the particular way in which the circuit is built. This
is part of the demodulating nature of the amplifier, which
results in an alternating input voltage being transformed into a
quasi-dc (rectified and filtered) output voltage.
The single supply nature of the AD606 results in common-mode
level of the inputs INHI and INLO being at about +2.5 V (us-
ing the recommended +5 V supply). In normal ac operation,
this bias level is developed internally and the input signal is
coupled in through dc blocking capacitors. Any residual dc
offset voltage in the first stage limits the logarithmic accuracy for
small inputs. In ac operation, this offset is automatically and
continuously nulled via a feedback path from the last stage, pro-
vided that the pins INHI and INLO are not shorted together, as
would be the case if transformer coupling were used for the signal.
While any logarithmic amplifier must eventually conform to the
basic equation shown above, which, with appropriate elabora-
tion, can also fully account for the effect of the signal waveform
on the effective intercept,
1
it is more convenient in RF applica-
tions to use a simpler expression. This simplification results
from first, assuming that the input is always sinusoidal, and
second, using a decibel representation for the input level. The
standard representation of RF levels is (incorrectly, in a log amp
context) in terms of power, specifically, decibels above 1 milli-
watt (dBm) with a presumed impedance level of 50 . That
being the case, we can rewrite the transfer function as
VVPP
LOG Y IN X
= ( –)
where it must be understood that P
IN
means the sinusoidal input
power level in a 50 system, expressed in dBm, and P
X
is the
intercept, also expressed in dBm. In this case, P
IN
and P
X
are
simple, dimensionless numbers. (P
X
is sometimes called the
“logarithmic offset,” for reasons which are obvious from the
above equation.) V
Y
is still defined as the logarithmic slope,
usually specified as so many millivolts per decibel, or mV/dB.
In the case of the AD606, the slope voltage, V
Y
, is nominally
750 mV when operating at V
POS
= 5 V. This can also be ex-
pressed as 37.5 mV/dB or 750 mV/decade; thus, the 80 dB
range equates to 3 V. Figure 1 shows the transfer function of the
AD606. The slope is closely proportional to V
POS
, and can more
generally be stated as V
Y
= 0.15 × V
POS.
Thus, in those applica-
tions where the scaling must be independent of supply voltage,
this must be stabilized to the required accuracy. In applications
where the output is applied to an A/D converter, the reference
VLOG – Volts DC
INPUT SIGNAL – dBm
4
0
+20
1
0.5
–80–100
2
1.5
2.5
3
3.5
0–20–40–60
SLOPE = 37.5mV/dB
INTERCEPT
AT –88.33dBm
Figure 1. Nominal Transfer Function
1
See, for example, the AD640 data sheet, which is published in Section 3 of
the Special Linear Reference Manual or Section 9.3 of the 1992 Amplifier
Applications Guide.
AD606
REV. B
–5–
ILOG and OPCM (output common, which is usually grounded).
The nominal slope at this point is 18.75 mV/dB (375 mV/
decade).
In applications where V
LOG
is taken to an A/D converter which
allows the use of an external reference, this reference input
should also be connected to the same +5 V supply. The power
supply voltage may be in the range +4.5 V to +5.5 V, providing
a range of slopes from nominally 33.75 mV/dB (675 mV/ de-
cade) to 41.25 mV/dB (825 mV/decade).
A buffer amplifier, having a gain of two, provides a final output
scaling at V
LOG
of 37.5 mV/dB (750 mV/decade). This low-
impedance output can run from close to ground to over +4 V
(using the recommended +5 V supply) and is tolerant of resis-
tive and capacitive loads. Further filtering is provided by a con-
jugate pole pair, formed by internal capacitors which are an
integral part of the output buffer. The corner frequency of the
overall filter is 2 MHz, and the 10%–90% rise time is 150 ns.
Later, we will show how the slope and intercept can be altered
using simple external adjustments. The direct buffer input
BFIN is used in these cases.
The last limiter output is available as complementary currents
from open collectors at pins LMHI and LMLO. These currents
are each 1.2 mA typical with LADJ grounded and may be con-
verted to voltages using external load resistors connected to
VPOS; typically, a 200 resistor is used on just one output.
The voltage gain is then over 90 dB, resulting in a hard-limited
output for all input levels down to the noise floor. The phasing
is such that the voltage at LMHI goes high when the input
(INHI to INLO) is positive. The overall delay time from the
signal inputs to the limiter outputs is 8 ns. Of particular impor-
tance is the phase stability of these outputs versus input level. At
50 MHz, the phase typically remains within ±4° from –70 dBm
to +5 dBm. The rise time of this output (essentially a square
wave) is about 1.2 ns, resulting in clean operation to more than
70 MHz.
for that converter should be a fractional part of V
POS
, if possible.
The slope is essentially independent of temperature.
The intercept P
X
is essentially independent of either the supply
voltage or temperature. However, the AD606 is not factory
calibrated, and both the slope and intercept may need to be
externally adjusted. Following calibration, the conformance to
an ideal logarithmic law will be found to be very close, particu-
larly at moderate frequencies (see Figure 14), and still accept-
able at the upper end of the frequency range (Figure 15).
CIRCUIT DESCRIPTION
Figure 2 is a block diagram of the AD606, which is a complete
logarithmic amplifier system in monolithic form. It uses a total
of nine limiting amplifiers in a “successive detection” scheme to
closely approximate a logarithmic response over a total dynamic
range of 90 dB (Figure 2). The signal input is differential, at
nodes INHI and INLO, and will usually be sinusoidal and ac
coupled. The source may be either differential or single-sided;
the input impedance is about 2.5 k in parallel with 2 pF. Seven
of the amplifier/detector stages handle inputs from –80 dBm
(32 µV rms) up to about –14 dBm (45 mV rms). The noise floor
is about –83 dBm (18 µV rms). Another two stages receive the
input attenuated by 22.3 dB, and respond to inputs up to
+10 dBm (707 mV rms). The gain of each of these stages is
11.15 dB and is accurately stabilized over temperature by a
precise biasing system.
The detectors provide full-wave rectification of the alternating
signal present at each limiter output. Their outputs are in the
form of currents, proportional to the supply voltage. Each cell
incorporates a low-pass filter pole, as the first step in recovering
the average value of the demodulated signal, which contains
appreciable energy at even harmonics of the input frequency. A
further real pole can be introduced by adding a capacitor be-
tween the summing node ISUM and VPOS. The summed de-
tector output currents are applied to a 6:1 reduction current
mirror. Its output at ILOG is scaled 2 µA/dB, and is converted
to voltage by an internal load resistor of 9.375 k between
REFERENCE
AND POWER-UP
ONE-POLE
FILTER
FINAL
LIMITER
MAIN SIGNAL PATH
11.15dB/STAGE
OFFSET-NULL
LOW-PASS FILTER
30pF
30pF
360kV
360kV
2pF
9.375kV
9.375kV
2pF
X2
TWO-POLE
SALLEN-KEY
FILTER
12mA/dB
2mA/dB
HIGH-END
DETECTORS
AD606
1.5kV
1.5kV
250V
30kV 30kV
910111213141516
1234567 8
INLO COMM ISUM ILOG BFIN VLOG OPCM LMLO
LMHILADJFIL2FIL1VPOSPRUPCOMMINHI
X1
Figure 2. Simplified Block Diagram

AD606JRZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Logarithmic Amplifiers 50 MHz 80dB DEMODULATING AMP
Lifecycle:
New from this manufacturer.
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