74ACT109SC Datasheet 74ACT109SC, 74AC109PC, 74ACT109SCX | P1-P3

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74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop

March 2007

74AC109, 74ACT109 Rev. 1.5

74AC109, 74ACT109

Dual JK

Positive Edge-Triggered Flip-Flop

Features

■

I

CC

reduced by 50%

■

Outputs source/sink 24mA

■

ACT109 has TTL-compatible inputs

General Description

The AC/ACT109 consists of two high-speed completely

independent transition clocked JK

flip-flops. The clocking

operation is independent of rise and fall times of the

clock waveform. The JK

design allows operation as a

D-Type flip-flop (refer to AC/ACT74 data sheet) by

connecting the J and K

inputs together.

Asynchronous Inputs:

– LOW input to S

D

(Set) sets Q to HIGH level

– LOW input to C

D

(Clear) sets Q to LOW level

– Clear and Set are independent of clock

– Simultaneous LOW on C

D

and S

D

makes both

Q and Q HIGH

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

Connection Diagram Pin Descriptions

Order

Number

Package

Number Package Description

74AC109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74AC109SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74AC109MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74ACT109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74AC109MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74ACT109PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Pin Names Description

J

1

, J

2

, K

1

, K

2

Data Inputs

CP

1

, CP

2

Clock Pulse Inputs

C

D1

, C

D2

Direct Clear Inputs

S

D1

, S

D2

Direct Set Inputs

Q

1

, Q

2

, Q

1

, Q

2

Outputs

FACT™ is a trademark of Fairchild Semiconductor Corporation

.

74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop

74AC109, 74ACT109 Rev. 1.5 2

Logic Symbols

Truth Table

Each half.

H

=

HIGH Voltage Level

L

=

LOW Voltage Level

=

LOW-to-HIGH Transition

X

=

Immaterial

Q

0

(Q

0

)

=

Previous Q

0

(Q

0

) before LOW-to-HIGH Transition of Clock

Logic Diagram

One half shown.

Please note that this diagram is provided only for the understanding of logic operations and should not be used to

estimate propagation delays.

Inputs Outputs

S

D

C

D

CP J K Q Q

LHXXXHL

HLXXXLH

LLXXXHH

HH LLLH

HH HL Toggle

HH LHQ

0

Q

0

HH HHHL

HHLXXQ

0

Q

0

IEEE/IEC

74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop

74AC109, 74ACT109 Rev. 1.5 3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Symbol Parameter Rating

V

CC

Supply Voltage –0.5V to +7.0V

I

IK

DC Input Diode Current

V

I

=

–0.5V

V

I

=

V

CC

+ 0.5V

–20mA

+20mA

V

I

DC Input Voltage –0.5V to V

CC

+ 0.5V

I

OK

DC Output Diode Current

V

O

=

–0.5V

V

O

=

V

CC

+ 0.5V

–20mA

+20mA

V

O

DC Output Voltage –0.5V to V

CC

+ 0.5V

I

O

DC Output Source or Sink Current ±50mA

I

CC

or I

GND

DC V

CC

or Ground Current per Output Pin ±50mA

T

STG

Storage Temperature –65°C to +150°C

T

J

Junction Temperature 140°C

Symbol Parameter Rating

V

CC

Supply Voltage

AC

ACT

2.0V to 6.0V

4.5V to 5.5V

V

I

Input Voltage 0V to V

CC

V

O

Output Voltage 0V to V

CC

T

A

Operating Temperature –40°C to +85°C

∆

V

/

∆

t Minimum Input Edge Rate, AC Devices:

V

IN

from 30% to 70% of V

CC

,

V

CC

@ 3.3V, 4.5V, 5.5V

125mV/ns

∆

V

/

∆

t Minimum Input Edge Rate, ACT Devices:

V

IN

from 0.8V to 2.0V, V

CC

@ 4.5V, 5.5V

125mV/ns

74ACT109SC

74ACT109SC

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