MC74HC393AFEL

© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 7
1 Publication Order Number:
MC74HC393A/D
MC74HC393A
Dual 4-Stage Binary Ripple
Counter
High−Performance Silicon−Gate CMOS
The MC74HC393A is identical in pinout to the LS393. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two independent 4−bit binary ripple counters
with parallel outputs from each counter stage. A ÷ 256 counter can be
obtained by cascading the two binary counters.
Internal flip−flops are triggered by high−to−low transitions of the
clock input. Reset for the counters is asynchronous and active−high.
State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and should not be used as clocks or as strobes except
when gated with the Clock of the HC393A.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the JEDEC Standard No. 7 A Requirements
Chip Complexity: 236 FETs or 59 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free and are RoHS Compliant
LOGIC DIAGRAM
Q1
Q2
Q3
Q4
CLOCK
RESET
1, 13
2, 12
3, 11
4, 10
5, 9
6, 8
PIN 14 = V
CC
PIN 7 = GND
BINARY
COUNTER
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
MARKING DIAGRAMS
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package
TSSOP−14
DT SUFFIX
CASE 948G
SOIC−14 NB
D SUFFIX
CASE 751A
HC393AG
AWLYWW
1
14
HC
393A
ALYWG
G
1
14
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Clock Reset Outputs
XH L
H L No Change
L L No Change
L No Change
L Advance to
Next State
TSSOP−14SOIC−14 NB
PIN ASSIGNMENT
11
12
13
14
8
9
105
4
3
2
1
7
6
Q2
b
Q1
b
RESET b
CLOCK b
V
CC
Q4
b
Q3
b
Q2
a
Q1
a
RESET a
CLOCK a
GND
Q3
a
Q4
a
MC74HC393A
http://onsemi.com
2
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
V
in
DC Input Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) –0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Current, per Pin ±25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±50 mA
P
D
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature –65 to +150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
260
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types –55 +125
_C
t
r
, t
f
Input Rise and Fall Time V
CC
= 2.0 V
V
CC
= 3.0 V
(Figure 1) V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
0
1000
600
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbo
l
Parameter Test Conditions
V
CC
V
Guaranteed Limit
Unit
–55 to
25_C
v85_C v125_C
V
IH
Minimum High−Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| v 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
V
IL
Maximum Low−Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| v 20 mA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
= V
IH
or V
IL
|I
out
| v 2.4 mA
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74HC393A
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) (continued)
Symbol Unit
Guaranteed Limit
V
CC
V
Test ConditionsParameter
Symbol Unit
v125_Cv85_C
–55 to
25_C
V
CC
V
Test ConditionsParameter
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
| v 2.4 mA
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
I
in
Maximum Input Leakage Current V
in
= V
CC
or GND 6.0 ±0.1 ±1.0 ±1.0
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0 mA
6.0 4 40 160
mA
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Symbo
l
Parameter
V
CC
V
Guaranteed Limit
Unit
–55 to
25_C
v85_C v125_C
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 3)
2.0
3.0
4.5
6.0
10
15
30
50
9
14
28
45
8
12
25
40
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Q1
(Figures 1 and 3)
2.0
3.0
4.5
6.0
70
40
24
20
80
45
30
26
90
50
36
31
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Q2
(Figures 1 and 3)
2.0
3.0
4.5
6.0
100
56
34
20
105
70
45
38
180
100
55
48
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Q3
(Figures 1 and 3)
2.0
3.0
4.5
6.0
130
80
44
37
150
105
55
47
180
130
70
58
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Q4
(Figures 1 and 3)
2.0
3.0
4.5
6.0
160
110
52
44
250
185
65
55
300
210
82
65
ns
t
PHL
Maximum Propagation Delay, Reset to any Q
(Figures 2 and 3)
2.0
3.0
4.5
6.0
80
48
30
26
95
65
38
33
110
75
50
43
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
C
in
Maximum Input Capacitance 10 10 10 pF
C
PD
Power Dissipation Capacitance (Per Counter)*
Typical @ 25°C, V
CC
= 5.0 V
pF
35
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
.

MC74HC393AFEL

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Counter ICs 2-6V Dual 4-Stage
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union