MC74HC393A
http://onsemi.com
4
TIMING REQUIREMENTS (Input t
r
= t
f
= 6 ns)
Symbo
Parameter
V
CC
V
Guaranteed Limit
Unit
–55 to
25_C
v85_C v125_C
t
rec
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
3.0
4.5
6.0
25
15
10
9
30
20
13
11
40
30
15
13
ns
t
w
Minimum Pulse Width, Clock
(Figure 1)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
ns
t
w
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
ns
t
r
, t
f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
PIN DESCRIPTIONS
INPUTS
Clock (Pins 1, 13)
Clock input. The internal flip−flops are toggled and the
counter state advances on high−to−low transitions of the
clock input.
OUTPUTS
Q1, Q2, Q3, Q4 (Pins 3, 4, 5, 6, 8, 9, 10, 11)
Parallel binary outputs Q4 is the most significant bit.
CONTROL INPUTS
Reset (Pins 2, 12)
Active−high, asynchronous reset. A separate reset is
provided for each counter. A high at the Reset input prevents
counting and forces all four outputs low.
