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4688D–RFID–03/07
U3280M
5. EEPROM
The EEPROM has a size of 512 bits and is organized as a 32 × 16-bit matrix. To read and write
data to and from the EEPROM, the serial interface must be used. The interface supports one
and two-byte write access and one to n-byte read access to the EEPROM.
5.1 EEPROM Operating Modes
The operating modes of the EEPROM are defined by the control byte. The control byte contains
the row address, the mode control bits and the read/not-write bit that is used to control the direc-
tion of the following transfer. A “0” defines the write access and a “1” defines a read access. The
five address bits select one of the 32 rows of EEPROM memory to be accessed. For complete
access the complete 16-bit word of the selected row is loaded into a buffer. The buffer must be
read or overwritten via the serial interface. The two mode control bits C1 and C2 define in which
order the access to the buffer is performed: high byte – low byte or low byte – high byte. The
EEPROM also supports auto-increment and auto-decrement read operations. After sending the
START address with the corresponding mode, consecutive memory cells can be read row by
row without transmission of the row addresses.
5.2 Write Operations
The EEPROM allows for 8-bit and 16-bit write operations. A write access starts with the START
condition followed by writing a write control byte and one or two data bytes from the master. It is
completed with the STOP condition from the master after the acknowledge cycle.
When the EEPROM receives the control byte, it loads the addressed memory cell into a 16-bit
read/write buffer. The following data bytes overwrite the buffer. The internal EEPROM program-
ming cycle is started by a STOP condition after the first or second data byte. During the
programming cycle, the addressed EEPROM cells are cleared and the contents of the buffer is
written back to the EEPROM cells. The complete erase-write cycle takes about 10 ms.
5.2.1 Acknowledge Polling
If the EEPROM is busy with an internal write cycle, all inputs are disabled and the EEPROM will
not acknowledge until the write cycle is finished. This can be used to determine when the write
cycle is complete. The master must perform acknowledge polling by sending a START condition
followed by the control byte. If the device is still busy with the write cycle, it will not return an
acknowledge and the master has to generate a STOP condition or perform further acknowledge
polling sequences.
If the cycle is complete, the device returns an acknowledge and the master can proceed with the
next read or write cycle.
