Si53152
Rev. 1.2 19
8. PCB Land Pattern
Figure 6. Si53152 24-Pin TDFN Land Pattern
Table 8. Si53152 24-Pin Land Pattern Dimensions
Dimension mm
C1 4.0
C2 4.0
E 0.50 BSC
X1 0.30
X2 2.70
Y1 0.80
Si53152
20 Rev. 1.2
Y2 2.70
Notes:
General
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least
Material Condition (LMC) is calculated based on a Fabrication Allowance of
0.05 mm.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all the
way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all pads.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Table 8. Si53152 24-Pin Land Pattern Dimensions (Continued)
Si53152
Rev. 1.2 21
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 1.0
Updated Features and Description.
Updated Table 2.
Updated Table 3.
Updated Section 4.1.
Revision 1.0 to Revision 1.1
Updated Features on page 1.
Updated Description on page 1.
Updated specs in Table 2, “AC Electrical
Specifications,” on page 5.
Revision 1.1 to Revision 1.2
Added condition for Clock Stabilization from Power-
up, T
STABLE
, in Table 2.

SI53152-A01AGMR

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Clock Buffer PCI-express Gen1/2/3 1:2 fan-out buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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