Si53152
Rev. 1.2 5
Table 2. AC Electrical Specifications
Parameter Symbol Test Condition Min Typ Max Unit
DIFFIN at 0.7 V
Input Frequency Range f
in
100 — 210 MHz
Rising and Falling Slew Rates for
Each Clock Output Signal in a
Given Differential Pair
T
R
/ T
F
Single ended measurement:
V
OL
= 0.175 to V
OH
= 0.525 V
(Averaged)
0.6 — 4 V/ns
Differential Input High Voltage V
IH
150 — — mV
Differential Input Low Voltage V
IL
— — –150 mV
Crossing Point Voltage at 0.7 V
Swing
V
OX
Single-ended measurement 250 — 550 mV
Vcross Variation over all edges V
OX
Single-ended measurement — — 140 mV
Differential Ringback Voltage V
RB
–100 — 100 mV
Time before ringback allowed T
STABLE
500 — — ps
Absolute Maximum Input
Voltage
V
MAX
—1.15V
Absolute Minimum Input
Voltage
V
MIN
–0.3 — — V
Duty Cycle for Each Clock
Output Signal in a Given
Differential Pair
T
DC
Measured at crossing point V
OX
45 — 55 %
Rise/Fall Matching T
RFM
Determined as a fraction of
2x(T
R
– T
F
)/(T
R
+ T
F
)
——20%
DIFF at 0.7 V
Duty Cycle T
DC
Measured at 0 V differential 45 — 55 %
Clock Skew T
SKEW
Measured at 0 V differential — — 50 ps
Additive Peak Jitter Pk-Pk 0 — 10 ps
Additive PCIe Gen 2
Phase Jitter
RMS
GEN2
10 kHz < F < 1.5 MHz 0 — 0.5 ps
1.5 MHz< F < Nyquist Rate 0 — 0.5 ps
Additive PCIe Gen 3
Phase Jitter
RMS
GEN3
Includes PLL BW 2–4 MHz
(CDR = 10 MHz)
0 — 0.10 ps
Additive PCIe Gen 4 Phase Jitter RMS
GEN4
PCIe Gen 4 — — 0.10 ps
Additive Cycle to Cycle Jitter T
CCJ
Measured at 0 V differential — — 50 ps
Long Term Accuracy L
ACC
Measured at 0 V differential — — 100 ppm
Notes:
1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
