CY28RS400OXCT Datasheet CY28RS400ZXCT, CY28RS400OXC, CY28RS400ZXC | P10-P12

CY28RS400

Document #: 38-07637 Rev. *B Page 10 of 19

CPU_STP# Assertion

The CPU_STP# signal is an active low input used for

synchronous stopping and starting the CPU output clocks

while the rest of the clock generator continues to function.

When the CPU_STP# pin is asserted, all CPU outputs that are

set with the SMBus configuration to be stoppable via assertion

of CPU_STP# will be stopped within two–six CPU clock

periods after being sampled by two rising edges of the internal

CPUC clock. The final states of the stopped CPU signals are

CPUT = HIGH and CPUC = LOW. There is no change to the

output drive current values during the stopped state. The

CPUT is driven HIGH with a current value equal to 6 x (Iref),

and the CPUC signal will be Hi-Z. When the control register

CPU_STP Hi-Z bit corresponding to the output of interest is

programmed to ‘1’, the final state of the stopped CPU clock is

low (due to external 50 ohm pull-down resistor), both CPUT

clock and CPUC clock outputs will not be driven.

CPU_STP# Deassertion

The deassertion of the CPU_STP# signal will cause all CPU

outputs that were stopped to resume normal operation in a

synchronous manner. Synchronous manner meaning that no

short or stretched clock pulses will be produce when the clock

resumes. The maximum latency from the deassertion to active

outputs is 2 - 6 CPU clock cycles.

Figure 4. Power-down Deassertion Timing Waveform

DOT96C

CPUC, 133MHz

CPUT, 133MHz

SRCC 100MHz

USB, 48MHz

DOT96T

SRCT 100MHz

Tstabl e

<1.8nS

PCI, 33MHz

REF

Tdrive_PWRDN#

<300µS, >200mV

CPU_STP#

CPUT

CPUC

Figure 5. CPU_STP# Assertion Waveform

CPU_STP#

CPUT

CPUC

CPUT Internal

Tdrive_CPU_STP#,10nS>200mV

CPUC Internal

Figure 6. CPU_STP# Deassertion Waveform

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CY28RS400

Document #: 38-07637 Rev. *B Page 11 of 19

CLK_REQ[0:1]# Description

The CLKREQ#[1:0] signals are active low input used for clean

stopping and starting selected SRC outputs. The outputs

controlled by CLKREQ#[1:0] are determined by the settings in

signal in that it’s state must remain unchanged during two

consecutive rising edges of DIFC to be recognized as a valid

assertion or de-assertion. (The assertion and de-assertion of

this signal is absolutely asynchronous).

CLK_REQ[0:1]# De-assertion [Low to High transition]

The impact of deasserting the CLKREQ#[1:0] pins is all DIF

outputs that are set in the control registers to stoppable via

de-assertion of CLKREQ#[1:0] are to be stopped after their

next transition. When the control register CLKREQ# drive

mode bit is programmed to ‘0’, the final state of all stopped

SRC signals is SRCT clock = High and SRCC = Low. There is

to be no change to the output drive current values, SRCT will

be driven high with a current value equal 6 x Iref,. When the

control register CLKREQ# drive mode bit is programmed to

‘1’, the final state of all stopped DIF signals is low, both SRCT

clock and SRCC clock outputs will not be driven.

CLK_REQ[0:1]# Assertion [High to Low transition]

All differential outputs that were stopped are to resume normal

operation in a glitch free manner. The maximum latency from

the assertion to active outputs is between two–six SRC clock

periods (two clocks are shown) with all SRC outputs resuming

simultaneously. If the CLKREQ# drive mode bit is

programmed to ‘1’ (three-state), the all stopped SRC outputs

must be driven high within 10 ns of CLKREQ#[1:0] assertion

to a voltage greater than 200 mV.

CPUC(Stoppable)

CPUT(Stoppable)

CPUC(Free Running

CPUT(Free Running

1.8mS

CPU_STOP#

Figure 7. CPU_STP#= Driven, CPU_PD = Driven

CPUC(Stoppable)

CPUT(Stoppable)

CPUC(Free Running)

CPUT(Free Running)

1.8mS

CPU_STOP#

Figure 8. CPU_STP# = Hi-Z, CPU_PD = Hi-Z

Figure 9. CLK_REQ#[0:1] Assertion/Deassertion Waveform

SRCT(stoppable)

SRCC(free running)

SRCT(free running)

CLKREQ#X

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CY28RS400

Document #: 38-07637 Rev. *B Page 12 of 19

FS_A, FS_B,FS_C

VTT_PWRGD#

PWRGD_VRM

VDD Clock Gen

Clock State

Clock Outputs

Clock VCO

0.2-0.3mS

Delay

State 0

State 2 State 3

Wait for

VTT_PWRGD#

Sample Sels

Off

State 1

Device is not affected,

VTT_PWRGD# is ignored

Figure 10. VTT_PWRGD# Timing Diagram

VTT_PWRGD# = Low

Delay

>0.25mS

Power Off

VDD_A = 2.0V

Sample

Inputs straps

Normal

Operation

Wait for <1.8ms

Enable Outputs

VTT_PWRGD# = toggle

VDD_A = off

Figure 11. Clock Generator Power-up/Run State Diagram

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P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

CY28RS400OXCT

Mfr. #:

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Manufacturer:

Cypress Semiconductor

Description:

IC CLK GEN CPU 266MHZ 2CIRC

Lifecycle:

New from this manufacturer.

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CY28RS400OXCT

CY28RS400OXCT

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