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CY28RS400OXCT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
CY28RS400
Document #: 38-07637 Rev. *B Page 4 of 19
27:20 Byte Count – 8 bits 20 Repeat start
28 Acknowledge from slave 27:21 Slave address – 7 bits
36:29 Data byte 1 – 8 bits 28 Read = 1
37 Acknowledge from slave 29 Acknowledge from slave
45:38 Data byte 2 – 8 bits 37:30 Byte Count from slave – 8 bits
46 Acknowledge from slave 38 Acknowledge
.... Data Byte /Slave Acknowledges 46:39 Data byte 1 from slave – 8 bits
.... Data Byte N –8 bits 47 Acknowledge
.... Acknowledge from slave 55:48 Data byte 2 from slave – 8 bits
.... Stop 56 Acknowledge
.... Data bytes from slave / Acknowledge
.... Data Byte N from slave – 8 bits
.... NOT Acknowledge
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol Byte Read Protocol
Bit Description Bit Description
1Start 1Start
8:2 Slave address – 7 bits 8:2 Slave address – 7 bits
9Write 9Write
10 Acknowledge from slave 10 Acknowledge from slave
18:11 Command Code – 8 bits 18:11 Command Code – 8 bits
19 Acknowledge from slave 19 Acknowledge from slave
27:20 Data byte – 8 bits 20 Repeated start
28 Acknowledge from slave 27:21 Slave address – 7 bits
29 Stop 28 Read
29 Acknowledge from slave
37:30 Data from slave – 8 bits
38 NOT Acknowledge
39 Stop
Table 4. Block Read and Block Write Protocol (continued)
Block Write Protocol Block Read Protocol
Bit Description Bit Description
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CY28RS400
Document #: 38-07637 Rev. *B Page 5 of 19
Control Registers
Byte 0:Control Register 0
Bit @Pup Name Description
7 1 SRC[T/C]5 SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
6 1 SRC[T/C]4 SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
5 1 SRC[T/C]3 SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
4 1 SRC[T/C]2 SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
3 1 SRC[T/C]1 SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
2 1 SRC [T/C]0 SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
1 1 SRCS[T/C]1 SRCS[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
0 1 SRCS[T/C]0 SRCS[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Byte 1: Control Register 1
Bit @Pup Name Description
7 1 REF2 REF2 Output Enable
0 = Disable, 1 = Enable
6 1 REF1 REF1 Output Enable
0 = Disable, 1 = Enable
5 1 REF0 REF0 Output Enable
0 = Disable, 1 = Enable
4 1 PCI0 PCI0 Output Enable
0 = Disable, 1 = Enable
3 1 USB_48 USB_48MHz Output Enable
0 = Disable, 1 = Enable
2 1 CPU[T/C]2 CPU[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
1 1 CPU[T/C]1 CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
0 1 CPU[T/C]0 CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Byte 2: Control Register 2
Bit @Pup Name Description
7 1 CPUT/C
SRCT/C
Spread Spectrum Selection
‘0’ = -0.35%
‘1’ = -0.50%
6 1 USB_48 48MHz Output Drive Strength
0 = 1x, 1 = 2x
5 1 PCI 33MHz Output Drive Strength
0 = 1x, 1 = 2x
4 0 Reserved Reserved
3 1 Reserved Reserved
20 CPU
SRC
CPU/SRC Spread Spectrum Enable
0 = Spread off, 1 = Spread on
1 1 Reserved Reserved
[+] Feedback
CY28RS400
Document #: 38-07637 Rev. *B Page 6 of 19
0 1 Reserved Reserved
Byte 3: Control Register 3
Bit @Pup Name Description
7 1 CLKREQ# CLKREQ# drive mode
0 = SRC clocks driven when stopped, 1 = SRC clocks tri-state when
stopped
6 0 CPU CPU pd drive mode
0 = CPU clocks driven when power down, 1 = CPU clocks tri-state
5 1 SRC SRC pd drive mode
0 = SRC clocks driven when power down, 1 = SRC clocks tri-state
4 0 CPU CPU_STOP# drive mode
0 = CPU clocks driven , 1 = CPU clocks tri-state
3 1 CPU2 Allow control of CPU2 with CPU_STOP#
0 = CPU2 is free running, 1 = CPU2 is stopped with CPU_STOP#
2 1 CPU1 Allow control of CPU1 with CPU_STOP#
0 = CPU1 is free running, 1 = CPU1 is stopped with CPU_STOP#
1 1 CPU0 Allow control of CPU0 with CPU_STOP#
0 = CPU0 is free running, 1 = CPU0 is stopped with CPU_STOP#
0 1 Reserved Reserved
Byte 4: Control Register 4
Bit @Pup Name Description
7 0 SRC[T/C]5 SRC[T/C]5 CLKREQ0 control
1 = SRC[T/C]5 stoppable by CLKREQ#0 pin
0 = SRC[T/C]5 free running
6 0 SRC[T/C]4 SRC[T/C]4 CLKREQ#0 control
1 = SRC[T/C]4 stoppable by CLKREQ#0 pin
0 = SRC[T/C]4 free running
5 0 SRC[T/C]3 SRC[T/C]3 CLKREQ#0 control
1 = SRC[T/C]3 stoppable by CLKREQ#0 pin
0 = SRC[T/C]3 free running
4 0 SRC[T/C]2 SRC[T/C]2 CLKREQ#0 control
1 = SRC[T/C]2 stoppable by CLKREQ#0 pin
0 = SRC[T/C]2 free running
3 0 SRC[T/C]1 SRC[T/C]1 CLKREQ#0 control
1 = SRC[T/C]1 stoppable by CLKREQ#0 pin
0 = SRC[T/C]1 free running
2 0 SRC[T/C]0 SRC[T/C]0 CLKREQ#0 control
1 = SRC[T/C]1 stoppable by CLKREQ#0 pin
0 = SRC[T/C]1 free running
1 1 Reserved Reserved
0 1 Reserved Reserved
Byte 5: Control Register 5
Bit @Pup Name Description
7 0 SRC[T/C]5 SRC[T/C]5 CLKREQ#1 control
1 = SRC[T/C]5 stoppable by CLKREQ#1 pin
0 = SRC[T/C]5 free running
6 0 SRC[T/C]4 SRC[T/C]4 CLKREQ#1 control
1 = SRC[T/C]4 stoppable by CLKREQ#1 pin
0 = SRC[T/C]4 free running
Byte 2: Control Register 2 (continued)
Bit @Pup Name Description
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

CY28RS400OXCT

Mfr. #:
Buy CY28RS400OXCT
Manufacturer:
Cypress Semiconductor
Description:
IC CLK GEN CPU 266MHZ 2CIRC
Lifecycle:
New from this manufacturer.
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