Production Data WM8524
w
PD, Rev 4.1, October 2011
13
AUDIO DATA FORMATS
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
Figure 6 Right Justified Audio Interface (24-bit word length)
In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 7 Left Justified Audio Interface (assuming n-bit word length)
In I
2
S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
WM8524 Production Data
w
PD, Rev 4.1, October 2011
14
Figure 8 I
2
S Justified Audio Interface (assuming n-bit word length)
DIGITAL AUDIO DATA SAMPLING RATES
The external master clock is applied directly to the MCLK input pin. In a system where there are a
number of possible sources for the reference clock, it is recommended that the clock source with the
lowest jitter be used for the master clock to optimise the performance of the WM8524.
The WM8524 has a detection circuit that automatically determines the relationship between the
master clock frequency (MCLK) and the sampling rate (LRCLK), to within ±32 system clock periods.
The MCLK must be synchronised with the LRCLK, although the device is tolerant of phase variations
or jitter on the MCLK.
If during sample rate change the ratio between MCLK and LRCLK varies more than once within 1026
LRCLK periods, then it is recommended that the device be taken into the standby state or the off
state before the sample rate change and held in standby until the sample rate change is complete.
This will ensure correct operation of the detection circuit on the return to the enabled state. For details
on the standby state, please refer to the Power up and down control section of the datasheet on page
16.
The DAC supports MCLK to LRCLK ratios of 128fs to 1152fs and sampling rates of 8kHz to 192kHz.
Table 3 shows typical master clock frequencies and sampling rates supported by the WM8524 DAC.
Sampling Rate
LRCLK
MASTER CLOCK FREQUENCY (MHz)
128fs 192fs 256fs 384fs 512fs 768fs 1152fs
8kHz Unavailable Unavailable 2.048 3.072 4.096 6.144 9.216
32kHz Unavailable Unavailable 8.192 12.288 16.384 24.576 36.864
44.1kHz Unavailable Unavailable 11.2896 16.9344 22.5792 33.8688 Unavailable
48kHz Unavailable Unavailable 12.288 18.432 24.576 36.864 Unavailable
88.2kHz 11.2896 16.9344 22.5792 33.8688 Unavailable Unavailable Unavailable
96kHz 12.288 18.432 24.576 36.864 Unavailable Unavailable Unavailable
176.4kHz 22.5792 33.8688 Unavailable Unavailable Unavailable Unavailable Unavailable
192kHz 24.576 36.864 Unavailable Unavailable Unavailable Unavailable Unavailable
Table 3 MCLK Frequencies and Audio Sample Rates
Production Data WM8524
w
PD, Rev 4.1, October 2011
15
HARDWARE CONTROL INTERFACE
The device is configured according to logic levels applied to the hardware control pins as described in
Table 4.
PIN NAME PIN
NUMBER
DESCRIPTION
MUTE¯¯¯¯¯ 11 Mute Control
0 = Mute
1 = Normal operation
AIFMODE 12 Audio Interface Mode
0 = 24-bit LJ
1 = 24-bit I
2
S
Z = 24-bit RJ
Table 4 Hardware Control Pin Configuration
MUTE
The MUTE¯¯¯¯¯ pin controls the DAC mute to both left and right channels. When the mute is asserted a
softmute is applied to ramp the signal down in 800 samples. When the mute is de-asserted the signal
returns to full scale in one step.

WM8524CGEDT/R

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Audio D/A Converter ICs Stereo DAC, 2Vrms
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet