Production Data WM8524
w
PD, Rev 4.1, October 2011
9
AUDIO INTERFACE TIMING – SLAVE MODE
BCLK
(input)
LRCLK
(input)
DACDAT
(input)
t
DS
t
DH
t
LRH
t
LRSU
t
BCH
t
BCL
t
BCY
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
Figure 2 Digital Audio Data Timing – Slave Mode
Test Conditions
LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, T
A
=+25
°
C, Slave Mode
PARAMETER SYMBOL MIN TYP MAX UNIT
Audio Data Input Timing Information
BCLK cycle time
t
BCY
27 ns
BCLK pulse width high
t
BCH
11 ns
BCLK pulse width low
t
BCL
11 ns
LRCLK set-up time to BCLK rising edge
t
LRSU
7 ns
LRCLK hold time from BCLK rising edge
t
LRH
5 ns
DACDAT hold time from LRCLK rising edge
t
DH
5 ns
DACDAT set-up time to BCLK rising edge
t
DS
7 ns
Table 1 Slave Mode Audio Interface Timing
Note:
BCLK period should always be greater than or equal to MCLK period.
