345RPLF Datasheet 345RPLF, 345RPLFT, 345RIPLFT | P4-P6

ICS345

TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER

IDT™ / ICS™

TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 4

ICS345 REV M 051310

Spread Spectrum Modulation

The ICS345 utilizes frequency modulation (FM) to distribute

energy over a range of frequencies. By modulating the

output clock frequencies, the device effectively lowers

energy across a broader range of frequencies; thus,

lowering a system’s electromagnetic interference (EMI). The

modulation rate is the time from transitioning from a

minimum frequency to a maximum frequency and then back

to the minimum.

Spread Spectrum Modulation can be applied as either

“center spread” or “down spread”. During center spread

modulation, the deviation from the target frequency is equal

in the positive and negative directions. The effective

average frequency is equal to the target frequency. In

applications where the clock is driving a component with a

maximum frequency rating, down spread should be applied.

In this case, the maximum frequency, including modulation,

is the target frequency. The effective average frequency is

less than the target frequency.

The ICS345 operates in both center spread and down

spread modes. For center spread, the frequency can be

modulated between ±0.125% to ±2.0%. For down spread,

the frequency can be modulated between -0.25% to -4.0%.

Both output frequency banks will utilize identical spread

spectrum percentage deviations and modulation rates, if a

common VCO frequency can be identified.

Spread Spectrum Modulation Rate

The spread spectrum modulation frequency applied to the

output clock frequency may occur at a variety of rates. For

applications requiring the driving of “down-circuit” PLLs,

Zero Delay Buffers, or those adhering to PCI standards, the

spread spectrum modulation rate should be set to 30-33

kHz. For other applications, a 120 kHz modulation option is

available.

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the ICS345. These ratings, which are

standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these

or any other conditions above those indicated in the operational sections of the specifications is not implied.

Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical

parameters are guaranteed only over the recommended operating temperature range.

Parameter Condition Min. Typ. Max. Units

Supply Voltage, VDD Referenced to GND 7 V

Inputs Referenced to GND -0.5 VDD+0.5 V

Clock Outputs Referenced to GND -0.5 VDD+0.5 V

Storage Temperature -65 150 ° C

Soldering Temperature Max 10 seconds 260 ° C

Junction Temperature 125 ° C

ICS345

TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER

IDT™ / ICS™

TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 5

ICS345 REV M 051310

Recommended Operation Conditions

DC Electrical Characteristics

Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C

Note 1: Example with 25 MHz crystal input with nine outputs of 33.3

MHz, no load, and VDD = 3.3 V.

Parameter Min. Typ. Max. Units

Ambient Operating Temperature (ICS345RP) 0 +70 ° C

Ambient Operating Temperature (ICS345RIP) -40 +85 ° C

Power Supply Voltage (measured in respect to GND) +3.15 +3.3 +3.45 V

Power Supply Ramp Time 4 ms

Parameter Symbol Conditions Min. Typ. Max. Units

Operating Voltage VDD 3.15 3.45 V

Operating Supply Current

Input High Voltage

IDD Configuration Dependent -

See VersaClock

Estimates

Nine 33.3333 MHz outs,

PDTS

= 1, no load, Note 1

23 mA

PDTS

= 0, no load, Note 1 20 µA

Input High Voltage V

S2:S0 2 V

Input Low Voltage V

S2:S0 0.4 V

Input High Voltage, PDTS

VDD-0.5 V

Input Low Voltage, PDTS

0.4 V

Input High Voltage V

ICLK VDD/2+1 V

Input Low Voltage V

ICLK VDD/2-1 V

Output High Voltage

(CMOS High)

= -4 mA VDD-0.4 V

Output High Voltage V

= -12 mA 2.4 V

Output Low Voltage V

= 12 mA 0.4 V

Short Circuit Current I

±70 mA

Nominal Output

Impedance

20 Ω

Internal Pull-up Resistor R

PUS

S2:S0, PDTS 250 kΩ

Internal Pull-down

Resistor

CLK outputs 525 kΩ

Input Capacitance C

Inputs 4 pF

ICS345

TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER

IDT™ / ICS™

TRIPLE PLL FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER 6

ICS345 REV M 051310

AC Electrical Characteristics

Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C

Note 1: Measured with 15 pF load.

Note 2: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%

Note 3: IDT test mode output occurs for first 170 clock cycles on CLK7 for each PLL powered up. PDTS

transition

high on select address change.

Note 4: The actual ppm error will be displayed in the VersaClock software when the programming file is generated

for the customer’s specific configuration. In general, zero ppm error can be achieved, but please note that the

device cannot improve upon the error of the input reference clock. For example, if the input crystal has 25 ppm error,

then the outputs will also have 25 ppm error.

Thermal Characteristics

Parameter Symbol Conditions Min. Typ. Max. Units

Input Frequency F

Fundamental crystal 5 27 MHz

Input clock 2 50 MHz

Output Frequency VDD=3.3 V 0.25 200 MHz

Output Rise Time t

20% to 80%, Note 1 1 ns

Output Fall Time t

80% to 20%, Note 1 1 ns

Duty Cycle Note 2 40 49-51 60 %

Output Frequency Synthesis

Error (Note 4)

Configuration Dependent 0 ppm

Power-up Time PLL lock-time from

power-up, Note 3

410ms

PDTS

goes high until stable

CLK output, Spread

Spectrum Off, Note 3

0.2 2 ms

PDTS

goes high until stable

CLK output, Spread

Spectrum On, Note 3

47ms

One Sigma Clock Period Jitter Configuration Dependent 50 ps

Maximum Absolute Jitter t

Deviation from Mean.

Configuration Dependent

+200 ps

Pin-to-Pin Skew Low Skew Outputs -250 250 ps

Parameter Symbol Conditions Min. Typ. Max. Units

Thermal Resistance Junction to

Ambient

Still air 135 ° C/W

1 m/s air flow 93 ° C/W

3 m/s air flow 78 ° C/W

Thermal Resistance Junction to Case θ

60 ° C/W

P1-P3 P4-P6 P7-P9

345RPLF

Mfr. #:

Buy 345RPLF

Manufacturer:

IDT

Description:

Clock Synthesizer / Jitter Cleaner VERSACLOCK SYNTHESIZER

Lifecycle:

New from this manufacturer.

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345RPLF

345RPLF

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