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71V3556SA133BQ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
6.42
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT
™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
19
NOTES:
1. Q (A
1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE
2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
Timing Waveform of Combined Read and Write Cycles
(1,2,3)
t
H
E
t
S
E
R
/
W
A
1
A
2
C
L
K
C
E
N
A
D
V
/
L
D
A
D
D
R
E
S
S
C
E
1
,
C
E
2
(
2
)
B
W
1
-
B
W
4
D
A
T
A
O
U
T
Q
(
A
3
)
Q
(
A
1
)
Q
(
A
6
)
Q
(
A
7
)
t
C
D
R
e
a
d
t
C
H
Z
5
2
8
1
d
r
w
0
8
W
r
i
t
e
t
C
L
Z
D
(
A
2
)
D
(
A
4
)
t
C
D
C
D
(
A
5
)
W
r
i
t
e
t
C
H
t
C
L
t
C
Y
C
t
H
W
t
S
W
t
H
A
t
S
A
A
4
A
3
t
H
C
t
S
C
t
S
D
t
H
D
t
H
A
D
V
t
S
A
D
V
A
6
A
7
A
8
A
5
A
9
D
A
T
A
I
N
t
H
B
t
S
B
O
E
R
e
a
d
R
e
a
d
,
,
,
6.42
20
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT
™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. Q (A
1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE
2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition
did not occur. All internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in two cycles before the actual data is presented to the SRAM.
Timing Waveform of CEN Operation
(1,2,3,4)
6.42
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT
™™
™™
™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
21
Timing Waveform of CS Operation
(1,2,3,4)
NOTES:
1. Q (A
1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3.
2. CE
2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not
occur. All internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
R
/
W
A
1
C
L
K
A
D
V
/
L
D
A
D
D
R
E
S
S
O
E
D
A
T
A
O
U
T
Q
(
A
1
)
t
C
D
t
C
L
Z
t
C
H
Z
t
C
D
C
t
C
H
t
C
L
t
C
Y
C
t
H
C
t
S
C
t
S
D
t
H
D
A
5
A
3
t
S
B
D
A
T
A
I
N
t
H
E
t
S
E
A
2
t
H
A
t
S
A
A
4
t
H
W
t
S
W
t
H
B
C
E
N
t
H
A
D
V
t
S
A
D
V
5
2
8
1
d
r
w
1
0
Q
(
A
2
)
Q
(
A
4
)
D
(
A
3
)
B
W
1
-
B
W
4
C
E
1
,
C
E
2
(
2
)
,
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

71V3556SA133BQ

Mfr. #:
Buy 71V3556SA133BQ
Manufacturer:
IDT
Description:
SRAM 4M X36 3.3V I/O SLOW ZBT
Lifecycle:
New from this manufacturer.
Delivery:
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