2001 Apr 17 7
NXP Semiconductors Product specification
8 W BTL or 2 × 4 W SE power amplifier TDA1517ATW
Notes to the characteristics
1. R
L
=4Ω, measured in Fig.4.
2. Output power is measured directly at the output pins of the IC.
3. Frequency response externally fixed.
4. V
ripple
=V
ripple(max)
= 2 V (p-p); R
S
=0Ω.
5. Noise voltage measured in a bandwidth of 20 Hz to 20 kHz.
6. Noise output voltage independent of R
S
.
7. V
i
=V
i(max)
= 1 V (RMS).
8. R
L
=8Ω, measured in Fig.3.
APPLICATION INFORMATION
handbook, full pagewidth
MGU304
15
41011
16
8
+OUT
OUT
PGND
SGND
9
100
nF
1000
μF
R
L
8 Ω
V
CC
TDA1517ATW
15 kΩ
10 kΩ
8.2
kΩ
15 kΩ
12
13
+IN1
3
18
17
MODE
5
470 nF
A
R
i
60 kΩ
B
V
CC
V
CC
STANDBY/
MUTE LOGIC
MICRO-
CONTROLLER
μc1
μc2
μc1
0
0
1
On
Mute
Standby
μc2
0
1
0
SHORT CIRCUIT
AND
TEMPERATURE
PROTECTION
input
reference
voltage
R
i
60 kΩ
Fig.3 BTL application block diagram.
2001 Apr 17 8
NXP Semiconductors Product specification
8 W BTL or 2 × 4 W SE power amplifier TDA1517ATW
handbook, full pagewidth
MGU305
15
41011
16
8
+OUT
OUT
PGND
SGND
9
100
nF
1000
μF
R
L
4 Ω
V
CC
TDA1517ATW
15 kΩ
10 kΩ
8.2
kΩ
15 kΩ
100
μF
1000 μF
R
L
4 Ω
1000 μF
12
13
IN1+
3
18
17
MODE
5
220 nF
A
R
i
60 kΩ
IN2
220 nF
B
V
CC
V
CC
STANDBY/
MUTE LOGIC
MICRO-
CONTROLLER
μc1
μc2
μc1
0
0
1
On
Mute
Standby
μc2
0
1
0
SHORT CIRCUIT
AND
TEMPERATURE
PROTECTION
input
reference
voltage
R
i
60 kΩ
Fig.4 SE application block diagram.
Test conditions
T
amb
=25°C; unless otherwise specified: V
P
=12V, BTL
application, f = 1 kHz, R
L
=8Ω, fixed gain = 26 dB, audio
band-pass: 22 Hz to 22 kHz. In the figures as a function of
frequency a band-pass of 10 Hz to 80 kHz was applied.
The BTL application block diagram is shown in Fig.3. The
PCB layout [which accommodates both the mono (BTL)
and stereo (single-ended) application] is shown in Fig.6.
Printed-Circuit Board (PCB) layout and grounding
For high system performance levels certain grounding
techniques are imperative. The input reference grounds
have to be tied to their respective source grounds and
must have separate traces from the power ground traces;
this will separate the large (output) signal currents from
interfering with the small AC input signals. The small signal
ground traces should be located physically as far as
possible from the power ground traces. Supply and output
traces should be as wide as possible for delivering
maximum output power.
Proper supply bypassing is critical for low noise
performance and high power supply rejection. The
respective capacitor locations should be as close as
possible to the device and grounded to the power ground.
Decoupling the power supply also prevents unwanted
oscillations. For suppressing higher frequency transients
(spikes) on the supply line a capacitor with low ESR
(typical 0.1 μF) has to be placed as close as possible to the
device. For suppressing lower frequency noise and ripple
signals, a large electrolytic capacitor (e.g. 1000 μF or
greater) must be placed close to the IC.
In single-ended (stereo) application a bypass capacitor
connected to pin SVR reduces the noise and ripple on the
midrail voltage. For good THD and noise performance a
low ESR capacitor is recommended.
Input configuration
It should be noted that the DC level of the input pins is
approximately 2.1 V; a coupling capacitor is therefore
necessary.
2001 Apr 17 9
NXP Semiconductors Product specification
8 W BTL or 2 × 4 W SE power amplifier TDA1517ATW
The formula for the cut-off frequency at the input is as
follows:
thus
As can be seen it is not necessary to use high capacitor
values for the input; so the delay during switch-on, which
is necessary for charging the input capacitors, can be
minimized. This results in a good low frequency response
and good switch-on behaviour.
In stereo applications (single-ended) coupling capacitors
on both input and output are necessary. It should be noted
that the outputs of both amplifiers are in opposite phase.
Built-in protection circuits
The IC contains two types of protection circuits:
Short-circuits the outputs to ground, the supply to
ground and across the load: short-circuit is detected and
controlled by a SOAR protection circuit
Thermal shut-down protection: the junction temperature
is measured by a temperature sensor. Thermal foldback
is activated at a junction temperature of >150 °C.
Output power
The output power as a function of supply voltage has been
measured on the output pins and at THD = 10%. The
maximum output power is limited by the maximum
allowable power dissipation and the maximum available
output current, 2.5 A repetitive peak current.
Supply voltage ripple rejection
The SVRR has been measured without an electrolytic
capacitor on pin 5 and at a bandwidth of 10 Hz to 80 kHz.
The curves for operating and mute condition (respectively)
were measured with R
source
=0Ω. Only in single-ended
applications is an electrolytic capacitor (e.g. 100 μF) on
pin 5 necessary to improve the SVRR behaviour.
Headroom
A typical music CD requires at least 12 dB (is factor 15.85)
dynamic headroom (compared with the average power
output) for passing the loudest portions without distortion.
The following calculation can be made for this application
at V
P
= 12 V and R
L
=8Ω: P
o
at THD = 0.1% is
approximately 5 W (see Fig.7).
Average listening level without any distortion yields:
The power dissipation can be derived from Fig.11 for 0 dB
and 12 dB headroom.
Table 1 Power rating
Thus for the average listening level (music power) a power
dissipation of 2.0 W can be used for the thermal PCB
calculation; see Section “Thermal behaviour (PCB design
considerations)”.
Mode pin
For the 3 functional modes: standby, mute and operate,
the MODE pin can be driven by a 3-state logic output
stage, e.g. a microcontroller with some extra components
for DC-level shifting; see Fig.10 for the respective
DC levels.
Standby mode is activated by a low DC level between
0 and 2 V. The power consumption of the IC will be
reduced to <0.12 mW.
Mute mode is activated by a DC level between
3.3 and 6.4 V. The outputs of the amplifier will be muted
(no audio output); however the amplifier is DC biased
and the DC level of the output pins stays at half the
supply voltage. The input coupling capacitors are
charged when in mute mode to avoid pop-noise.
The IC will be in the operating condition when the
voltage at pin MODE is between 8.5 V and V
CC
.
Switch-on/switch-off
To avoid audible plops during switch-on and switch-off of
the supply voltage, the MODE pin has to be set in standby
condition (V
CC
level) before the voltage is applied
(switch-on) or removed (switch-off). The input and SVRR
capacitors are smoothly charged during mute mode.
The turn-on and turn-off time can be influenced by an
RC-circuit connected to the MODE pin. Switching the
device or the MODE pin rapidly on and off may cause ‘click
and pop’ noise. This can be prevented by proper timing on
the MODE pin. Further improvement in the BTL application
can be obtained by connecting an electrolytic capacitor
(e.g. 100 μF) between the SVRR pin and signal ground.
f
IC
1
2 π× R
i
C
i
×
------------------------------
=
f
IC
1
2 π× 30× 10
3
× 470× 10
9
×
------------------------------------------------------------------------------
11 Hz==
RATING HEADROOM
POWER
DISSIPATION
P
o
=5W
(THD = 0.1%)
0dB 3.5W
12 dB 2.0 W
P
ALL
P
tot
factor
-----------------
5
15.85
---------------
315 mW===

TDA1517ATW/N1,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC AMP AUDIO PWR 8W STER 20TSSOP
Lifecycle:
New from this manufacturer.
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