11
ATF1500ABV
0723I–08/01
Power-up Reset The ATF1500ABV’s registers are designed to reset during power-up. At a point delayed
slightly from V
CC
crossing V
RST
, all registers will be reset to the low state. As a result, the reg-
istered output state will always be low on power-up.
This feature is critical for state machine initialization. However, due to the asynchronous
nature of reset and the uncertainty of how V
CC
actually rises in the system, the following condi-
tions are required:
1. The V
CC
rise must be monotonic, from below 0.7 volts.
2. Signals from which clocks are derived must remain stable during T
PR
.
3. After T
PR
occurs, all input and feedback setup times must be met before driving the
clock signal high.
Power-down
Mode
The ATF1500ABV includes an optional pin-controlled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply
current is reduced to less than 10 µA. During power-down, all output data and internal logic
states are latched and held. Therefore, all registered and combinatorial output data remain
valid. Any outputs that were in a High-Z state at the onset of power-down will remain at
High-Z. During power-down, all input signals except the power-down pin are blocked. Input
and I/O hold latches remain active to ensure that pins do not float to indeterminate levels, fur-
ther reducing system power. The power-down pin feature is enabled in the logic design file.
Designs using the power-down pin may not use the PD pin logic array input. However, all
other PD pin macrocell resources may still be used, including the buried feedback and fold-
back product term array inputs.
Register
Preload
The ATF1500ABV’s registers are provided with circuitry to allow loading of each register with
either a high or a low. This feature will simplify testing since any state can be forced into the
registers to control test sequencing. A JEDEC file with preload is generated when a source file
with preload vectors is compiled. Once downloaded, the JEDEC file preload sequence will be
done automatically when vectors are run by any approved programmers. The preload mode is
enabled by raising an input pin to a high voltage level. Contact Atmel PLD Applications for
PRELOAD pin assignments, timing and voltage requirements.
Parameter Description Typ Max Units
T
PR
Power-up
Reset Time
210 µs
V
RST
Power-up
Reset
Voltage
2.2 2.7 V
