6
ATF1500ABV
0723I–08/01
Flip-flop The ATF1500ABV’s flip-flop has very flexible data and control functions. The data input can
come from either the XOR gate or from a separate product term. Selecting the separate prod-
uct term allows creation of a buried registered feedback within a combinatorial output
macrocell.
In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-through
latch. In this mode, data passes through when the clock is high and is latched when the clock
is low.
The clock itself can be either the global CLK pin or an individual product term. The flip-flop
changes state on the clock’s rising edge. When the CLK pin is used as the clock, one of the
macrocell product terms can be selected as a clock enable. When the clock enable function is
active and the enable signal (product term) is low, all clock edges are ignored.
The flip-flop’s asynchronous reset signal (AR) can be either the pin global clear (GCLR), a
product term, or always off. AR can also be a logic OR of GCLR with a product term. The
asynchronous preset (AP) can be a product term or always off.
Output Select
and Enable
The ATF1500ABV macrocell output can be selected as registered or combinatorial. When the
output is registered, the same registered signal is fed back internally to the global bus. When
the output is combinatorial, the buried feedback can be either the same combinatorial signal or
it can be the register output if the separate product term is chosen as the flip-flop input.
The output enable multiplexer (MOE) controls the output enable signals. Any buffer can be
permanently enabled for simple output operation. Buffers can also be permanently disabled to
allow use of the pin as an input. In this configuration all the macrocell resources are still avail-
able, including the buried feedback, expander and CASCADE logic.
The output enable for each macrocell can also be selected as either of the two OE pins or as
an individual product term.
Global/Regional
Buses
The global bus contains all input and I/O pin signals as well as the buried feedback signal from
all 32 macrocells. Together with the complement of each signal, this provides a 68-bit bus as
input to every product term. Having the entire global bus available to each macrocell elimi-
nates any potential routing problems. With this architecture designs can be modified without
requiring pinout changes.
Each macrocell also generates a foldback product term. This signal goes to the regional bus,
and is available to 16 macrocells. The foldback is an inverse polarity of one of the macrocell’s
product terms. The 16 foldback terms in each region allow generation of high fan-in sum terms
(up to 21 product terms) with little additional delay.
