AS2702-20 Datasheet AS2702-20T, AS2702-16T, AS2702-20 | P10-P12

AS2702 – AS-Interface Slave IC

Revision 1.3, 21-Aug-08 Page 10 of 13

Operation Status Pins LED1 and LED2

Pins LED1 and LED2 are both equipped with a low-side open-drain output switch plus a passive high-side current source with a

nom. 10µA pull-up current capability. They will each have an LED load connected to UOUT, which will flag the operation status of

the slave device, according to the following table:

Output LED1 Output LED2 Flagging Priority Slave Device Reason

(green LED

connected)

(red LED

connected)

(1 = highest, …,

4 = lowest)

Operation Status

off off Supply voltage off No supply voltage

on off Regular operation

off of 4 No data communication Regular, non-zero slave address

coded; data comm. watchdog

triggered

blinks on 3 No regular slave address

coded

Slave address = default zero

blinks blinks (alternating

with LED1)

2 Hardware failure in

sensor/actuator circuitry

Input PFAULT = L

off blinks 1 External RESET or

overload at UOUT pin

DSTBn = L to RESET, or UOUT

switched-off due to overload

(LED1 and LED2 both also feature an input stage, to simplify component test and shorten test time of the slave device.)

The dc- and timing parameters of pins LED1 and LED2 are specified as follows:

Symbol Parameter Min Max Unit Note

ILED Sink current @ output L 10 mA VOUT = 1V

IOUTHI Leakage current @ output off -10 10 µA VOUT = 5V

VIN Acceptable input voltage @ output off -0.3 40 V

fBLINK Blinking frequency 2 3 Hz

Data Communication Watchdog

AS2702 is equipped with a watchdog timer to supervise data communication by monitoring the strobe signals at pins DSTBn and

PSTBn.

If a parameter or data strobe is not followed by a consecutive strobe within a time period of 50 … 100ms, the watchdog is triggered

and initiates a ‘soft’ reset, see section Reset.

Reset

There are 2 categories of reset-events, leading to 2 slightly different reset-conditions of the slave device:

1 A ‘hard’ reset taking place at power-up and power-down of supply-voltages U5R and UOUT.

At power-up the slave device leaves reset-condition as soon as U5R has passed 3.75V and

UOUT has passed VCOMOFF =

nom. 10V.

At power-down the slave device is forced into reset-condition as soon as U5R drops below 3.75V.

(Tolerance of the threshold voltages referred to is ± 5 %)

2 A ‘soft’ reset, resulting from one of the following events:

2.1 Data strobe pin DSTBn is kept L for more than 100ms;

2.2 Master command ‘RESET SLAVE’ is received;

2.3 Master command ‘RESET BROADCAST’ is received;

2.4 The communication watchdog is triggered.

AS2702 – AS-Interface Slave IC

Revision 1.3, 21-Aug-08 Page 11 of 13

A ‘hard’ reset event conditions the slave device as follows:

• Internal states (counters, flags, …) are reset

• The slave device’s receiver is desynchronized from the AS-Interface bus

• The low-side open-drain output stages at ports D3, …, D0 and ports P3, …, P0 are switched off

• Any test mode will be cancelled

A ‘soft’ reset has the following consequences:

• A regular, nominal 6µs L-phase strobe is generated on both the DSTBn and PSTBn pin

• The low-side open-drain output stages at ports D3, …, D0 and ports P3, …, P0 are switched off

• Internal states (counters, flags, …) are rest, however the following states and operations are not affected:

– the timer function which controls blinking of LED1 and LED2

– the data communication

– any test mode

– any EEPROM write operation

Remark:

If UOUT drops below VCOMOFF = nom. 10V data communication with the AS-Interface bus is aborted by the receiver or transmitter

of the slave device. As long as U5R does not drop below 3.75V in this situation, no ‘hard’ reset takes place; however the data

communication watchdog will be triggered (unless disabled) and a ‘soft’ reset will result.

EEPROM

AS2702 has a 16 x 8 Bits serial interface EEPROM on board to store the slave unit’s address and set-up data in a non-volatile

fashion.

The EEPROM stores the following data:

EEPROM-Address Data Relevant No. of Bits Programmed by Note

0, 1 Slave Address 5 + 1 Master (Initialization) 1

2 Settings (EID1) 4 Master (Initialization)

3 Settings (IO-Conf.) 5 Slave unit manufacturer

4 Settings (ID) 5 Slave unit manufacturer

5 Settings (EID2) 5 Slave unit manufacturer

6 Settings (Control-Code) 5 Slave unit manufacturer

Note:

1 6 Bits (A4, …, A0 + Sel-bit) in extended address mode: 62 slaves addressable;

5 Bits (A4, …, A0) in non-extended address mode: 31 slaves addressable

Obviously the capacity of the EEPROM is only partially used.

Reading and writing of the EEPROM is performed bytewise and trough temporary, volatile registers.

Writing of data from the volatile register into the EEPROM takes about 10ms per byte, whereas reading takes less than 1ms per

byte.

Upon RESET the EEPROM info is read into temporary register, including the slave’s address which has been written redundantly

into EEPROM locations 0 and 1 before.

The temporary registers receiving the address are compared for similarity; in case of non-similarity – which e.g. may have been

caused by a supply voltage dip during address writing – the slave will flag non-regular operation status/slave address zero.

AS2702 – AS-Interface Slave IC

Revision 1.3, 21-Aug-08 Page 12 of 13

AS-Interface Bus Communication

All slaves connected to an AS-Interface bus are sequentially and cyclicly called by the master in a string of individual transactions

between the master and each slave unit.

A transaction consists of a 14 bits master request, typically containing the slave’s address as well as data or parameter info, and an

immediate acknowledging slave response of 7 bits.

The 14 bits master request – apart from Start Bit ST = 0 and End Bit EB = 1 – has the following contents:

• 1 Control Bit CB: CB = 0 stands for data transfer (typ. data or parameters)

CB = 1 identifies command-type requests

• 5 Address Bits: A4, …, A0

• 5 Information Bits: I4, …, I0 (typ. data or parameters)

• 1 Parity Bit PB

AS2702 allows for up to 62 slaves on the same AS-Interface bus; this requires a slave address extended to 6 bits, hence an extra

bit beyond A4, …, A0.

Information bit I3 is used as the 6

address bit in this so-called extended address mode. It is called Sel-bit, as it is perceived as to

select between A-slave (Sel = 0) and B-slave (Sel = 1) at address location A4, …, A0.

In non-extended address mode AS2702 is addressed with A4, …, A0 only – for a max. total of 31 slaves per AS-Interface bus

system, and is system compatible with existing slave device AS2701A.

The 7 bits slave response – apart from Start Bit ST = 0 and End Bit EB = 1 – has the following contents:

• 4 Information Bits: I4, …, I0 (typ. data or parameters)

• 1 Parity Bit PB

Application Support

For general information and documentation on the AS-Interface concept you may contact the AS-Interface Association:

AS-International Association

Zum Taubengarten 52

D-63571 Gelnhausen

Tel.: +49-6051-473212

Fax: +49-6051-473282

e-mail: info@as-interface.net

http://www.as-interface.net

Ordering Information

AS2702-20T Package: SOIC 20; delivery: tape & reel

AS2702-16T Package: SOIC 16W; delivery: tape & reel; no parameter port available

AS2702-20 Package: SOIC 20; delivery: tubes

AS2702-16 Package: SOIC 16W; delivery: tubes; no parameter port available

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

AS2702-20

Mfr. #:

Buy AS2702-20

Manufacturer:

ams

Description:

Sensor Interface AS-Interface Slave IC

Lifecycle:

New from this manufacturer.

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AS2702-20

AS2702-20

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