FM75 Low-Voltage Two-Wire Digital Temperature Sensor with Thermal Alarm
© 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com
FM75 Rev. 1.0.8 13
Timing Diagrams
Figure 11. Pointer Set Followed by Immediate Read from a Two-byte Register
(Temperature, T
OS
, or T
HYST
Register)
Figure 12. Two-byte Read from Preset Pointer Location (Temperature, T
OS
, or T
HYST
Register)
Figure 13. One-byte Read from Configuration Register with Preset Pointer
000
000
P1 P0
A2 A1 A0
Address Byte Pointer Byte
1100
R/W
S
A
A
Ack
from
FM75
Ack
from
aTS75
. . . .
. . . .
Note: This segment of this timing diagram is a generic
pointer set cycle that must be followed by either an
immediate read cycle or write cycle, as shown in this
figure and in figures 10, 11, and 12.
SCL
SDA
Most Significant Data
Byte
from FM75
Least Significant Data Byte
(from FM75)
D7 D6 D5
D4
D3 D2 D1 D0
A2 A1
A0
D7 D6 D5
D4
000
0
Address Byte
110
0
R/W
S
PAA
N
Ack
from
FM75
Ack
from
Master
No Ack
from
Master
Repeat
Start
from
Master
. . .
. . .
SCL
SDA
D7 D6 D5 D4 D3 D2 D1 D0A2 A1 A0 D7 D6 D5 D4 0 0 0 0
Address
Byte
Most Significant Data
Byte
(from FM75)
110 0 R/W
Least Significant Data
Byte
(from FM75)
S PAAN
Ack
from
FM75
Ack
from
Master
No Ack
from
Master
SCL
SDA
X D6D5D4D3D2D1D0A2 A1 A0
Address Byte
Data Byte
from FM75
110 0 R/W
S PAN
Ack
from
FM75
No Ack
from
Master
SCL
SDA
