CS51031
http://onsemi.com
5
Startup
The CS51031 has an externally programmable Soft−Start
feature that allows the output voltage to come up slowly,
preventing voltage overshoot on the output.
At startup, the voltage on all pins is zero. As V
CC
rises, the
V
C
voltage along with the internal resistor R
G
keeps the
P−Ch FET off. As V
CC
and V
C
continue to rise, the oscillator
capacitor (C
OSC
) and the Soft−Start/Fault Timing capacitor
(CS) charges via internal current sources. C
OSC
gets charged
by the current source IC and CS gets charged by the I
T
source
combination described by:
I
CS
+ I
T
*
ǒ
I
T
55
)
I
T
5
Ǔ
The internal Holdoff Comparator ensures that the external
P−Ch FET is off until V
CS
> 0.7 V, preventing the GATE
flip−flop (F2) from being set. This allows the oscillator to
reach its operating frequency before enabling the drive
output. Soft−Start is obtained by clamping the V
FB
comparator’s (A6) reference input to approximately 1/2 of
the voltage at the CS pin during startup, permitting the
control loop and the output voltage to slowly increase. Once
the CS pin charges above the Holdoff Comparator trip point
of 0.7 V, the low feedback to the V
FB
Comparator sets the
GATE flip−flop during C
OSC
’s charge cycle. Once the
GATE flip−flop is set, V
GATE
goes low and turns on the
P−Ch FET. When V
CS
exceeds 2.3 V, the CS charge sense
comparator (A4) sets the V
FB
comparator reference to
1.25 V completing the startup cycle.
Lossless Short Circuit Protection
The CS51031 has “lossless” short circuit protection since
there is no current sense resistor required. When the voltage
at the CS pin (the fault timing capacitor voltage) reaches
2.5 V during startup, the fault timing circuitry is enabled by
A2. During normal operation the CS voltage is 2.6 V. During
a short circuit or a transient condition, the output voltage
moves lower and the voltage at V
FB
drops. If V
FB
drops
below 1.15 V, the output of the fault comparator goes high
and the CS51031 goes into a fast discharge mode. The fault
timing capacitor, CS, discharges to 2.4 V. If the V
FB
voltage
is still below 1.15 V when the CS pin reaches 2.4 V, a valid
fault condition has been detected. The slow discharge
comparator output goes high and enables gate G5 which sets
the slow discharge flip−flop. The V
GATE
flip−flop resets and
the output switch is turned off. The fault timing capacitor is
slowly discharged to 1.5 V. The CS51031 then enters a
normal startup routine. If the fault is still present when the
fault timing capacitor voltage reaches 2.5 V, the fast and
slow discharge cycles repeat as shown in figure 3.
If the V
FB
voltage is above 1.15 V when CS reaches 2.4 V
a fault condition is not detected, normal operation resumes
and CS charges back to 2.6 V. This reduces the chance of
erroneously detecting a load transient as a fault condition.
Figure 3. Voltage on Start Capacitor (V
GS
), the Gate (V
GATE
), and in the
Feedback Loop (V
), During Startup, Normal and Fault Conditions
1.15 V
1.25 V
0 V
1.5 V
2.4 V
2.5
0 V
V
CS
GATE
V
FB
START NORMAL OPERATION
FAULT
td1T
START
t
FAULT
t
RESTART
td2 t
FAULT
S1
S2 S1
S2
S3
S3
S1
S2
S3
S3
0.7 V
