CS51031
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7
4) Inductor Selection
The inductor value is chosen for continuous mode
operation down to 0.3 Amps.
The ripple current DI = 2 × I
OUT
min = 2 × 0.3 A = 0.6 A.
L
min
+
(
V
OUT
) V
D
)
T
OFF(max)
DI
+
5.6 V 3.0 ms
0.6 A
+ 28 mH
This is the minimum value of inductor to keep the ripple
current < 0.6 A during normal operation.
A smaller inductor will result in larger ripple current.
Ripple current at a minimum off time is:
DI +
(
V
OUT
) V
F
)
T
OFF(min)
L
MIN
+
5.6 V 2.0 ms
28 mH
+ 0.4 A
The core must not saturate with the maximum expected
current, here given by:
I
MAX
+ I
OUT
) DIń2 + 3.0 A ) 0.4 Ań2 + 3.2 A
5) Output Capacitor
The output capacitor and the inductor form a low pass
filter. The output capacitor should have a low ESL and ESR.
Low impedance aluminum electrolytic, tantalum or organic
semiconductor capacitors are a good choice for an output
capacitor. Low impedance aluminum are less expensive.
Solid tantalum chip capacitors are available from a number
of suppliers and are the best choice for surface mount
applications.
The output capacitor limits the output ripple voltage. The
CS51031 needs a maximum of 20 mV of output ripple for
the feedback comparator to change state. If we assume that
all the inductor ripple current flows through the output
capacitor and that it is an ideal capacitor (i.e. zero ESR), the
minimum capacitance needed to limit the output ripple to
50 mV peak−to−peak is given by:
C +
DI
8.0 f
SW
DV
+
0.6 A
8.0
(
200 10
3
Hz
)
(
50 10
*3
V
)
+ 7.5mF
The minimum ESR needed to limit the output voltage
ripple to 50 mV peak−to−peak is:
ESR +
DV
DI
+
50 10
*3
0.6 A
+ 83 mW
The output capacitor should be chosen so that its ESR is
less than 83 mW.
During the minimum off time, the ripple current is 0.4 A
and the output voltage ripple will be:
DV + ESR DI + 83m W 0.4 + 33 mV
6) V
FB
Divider
V
OUT
+ 1.25 V
ǒ
R1 ) R2
R2
Ǔ
+ 1.25 V
ǒ
R1
R2
) 1.0
Ǔ
The input bias current to the comparator is 4.0 mA. The
resistor divider current should be considerably higher than
this to ensure that there is sufficient bias current. If we
choose the divider current to be at least 250 times the bias
current this permits a divider current of 1.0 mA and
simplifies the calculations.
5.0 V
1.0 mA
+ R1 ) R2 + 5.0 KW
Let R2 = 1.0 K
Rearranging the divider equation gives:
1 + R2
V
OUT
* 1.0
+ 1.0 kW
5.0 V
* 1.0
+ 3.0 kW
7) Divider Bypass Capacitor C
RR
Since the feedback resistors divide the output voltage by
a factor of 4.0, i.e. 5.0 V/1.25 V = 4.0, it follows that the
output ripple is also divided by four. This would require that
the output ripple be at least 60 mV (4.0 × 15 mV) to trip the
feedback comparator. We use a capacitor C
RR
to act as an
AC short.
The ripple voltage frequency is equal to the switching
frequency so we choose C
RR
= 1.0 nF.
8) Soft−Start and Fault Timing Capacitor CS
CS performs several important functions. First it provides
a delay time for load transients so that the IC does not enter
a fault mode every time the load changes abruptly. Secondly
it disables the fault circuitry during startup, it also provides
Soft−Start by clamping the reference voltage during startup,
allowing it to rise slowly, and, finally it controls the hiccup
short circuit protection circuitry. This reduces the duty cycle
to approximately 0.035 during short circuit conditions.
An important consideration in calculating CS is that it’s
voltage does not reach 2.5 V (the voltage at which the fault
detect circuitry is enabled) before V
FB
reaches 1.15 V
otherwise the power supply will never start.
If the V
FB
pin reaches 1.15 V, the fault timing comparator
will discharge CS and the supply will not start. For the V
FB
voltage to reach 1.15 V the output voltage must be at least
4 × 1.15 = 4.6 V.
If we choose an arbitrary startup time of 900 ms, the value
of CS is:
t
Startup
+
CS 2.5 V
I
Charge
CS
min
+
900 ms 264 mA
2.5 V
+ 950 nF ^ 0.1 mF
